about us

The primary objective of the laboratory is to develop techniques useful for low power and high performance advanced nanoelectronics device, circuits, architecture and system. The current research activities/interests of the laboratory include all levels of the design ranging from the device to system level. More specifically, they can be categorized as:

1)      Modeling planar and non-planar MOSFET  device structures

2)      Process Variations and Process Tolerance

3)      Low power Design of digital systems in all levels

4)      Power supply noise modeling and tolerance

5)      Optical interconnections and device structures

6)      System on chip and network on chip

The research activities of the group performed as the digital division of the IC Design Laboratory in 2001 when this laboratory was established. By growing the range of research activities of the group finally at the beginning of 2005, The Low-Power High-Performance Nanosystems Laboratory was founded. The lab which is one of the labs affiliated to the Nanoelectronics Center of Excellence has many collaborations with other affiliated labs of this center.