journal

1. M. Daneshtalab, M. Ebrahimi, S. Mohammadi, and A. Afzali-Kusha, “Low-distance Path-based Multicast Routing Algorithm for Network-on-Chips,” Accepted for Publication in IET Proceedings of Computer and Digital Techniques

2. M. Saneei, A. Afzali-Kusha, and M. Pedram, “Two High Performance and Low Power Serial Communication Interfaces for On-chip Interconnects,” Canadian Journal of Electrical and Computer Engineering, July 2008.

3. G. Razavipour, A. Afzali-Kusha, and M. Pedram, “Design and Analysis of Two Low Power SRAM Cell Structures,” IEEE Transactions on Very Large Scale Integrated Circuits, July 2008.

4. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “Sign Bit Reduction Encoding For Low Power Applications,” Journal of VLSI Signal Processing Systems, September 2008.

5. M. Mottaghi-Dastjerdi, A. Afzali-Kusha, and M. Pedram, “BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture,” IEEE Transactions on Very Large Scale Integrated Circuits, 2009, vol. 17, no. 2, pp. 302 – 306.

6. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “A Low-Power High Throughput Link Splitting Router for NoCs,” Journal of Zhejiang University-SCIENCE A, 2008, vol. 9, no. 12, pp. 1708 – 1714.

7. M. Samadi and A. Afzali-Kusha, “Dynamic power management with fuzzy decision support system,” IEICE Electronics Express, August 2008, vol. 5, no. 19, pp. 789 – 795.

8. A. Abbasian, S. Hatami, A. Afzali-Kusha, and M. Pedram, "Wavelet-Based Dynamic Power Management for Non-stationary Service Requests," ACM Transactions on Design Automation of Electronic Systems, 2008, vol. 13, no. 1, article 13, pp. 13:1-13:41.

9. H. Parehdeh-Afshar, M. Saneei, A. Afzali-Kusha, and M. Pedram, "Fast INC-XOR codec for low-power address buses," IET Comput. Digit. Tech., 2007, vol. 1, no. 5, pp. 625-631.

10.  A. Mehran, S. Saeidi, A. Khademzadeh, and A. Afzali-Kusha, "Spiral: A heuristic mapping algorithm for network on chip," IEICE Electronics Express, 2007, vol. 4, no. 15, August 10, 2007, pp. 478-484.

11. F. Aezinia and A. Afzali-Kusha, "Low Power High Performance Level Converter for Dual Supply Voltage Systems," IEICE Electronics Express, vol. 4 (2007), no. 9, pp. 306-311.

12. K. Shoajee, M. Gholipour, A. Afzali-Kusha, and M. Nourani, “Comparative study of asynchronous pipeline design methods”, IEICE Electronics Express, vol. 3, no. 8, April 2006, pp. 163–171.

13. A. Amirabadi, Y. Mortazavi, A. Afzali-Kusha, and M. Nourani, “Clock Delayed Domino Logic with Efficient Variable Threshold Voltage Keeper,” Accepted for publication in IEEE Transaction on Very Large Scale Integrated Circuits, October 2006.

14. S. Sharifi, J. Jaffari, M. Hosseinabady, A. Afzali-Kusha, and Z. Navabi, “Scan-Based Structure with Reduced Static and Dynamic Power Consumption,” to appear in Journal of Low Power Electronics, vol. 2, no. 3, Dec. 2006, pp. 477-487.

15. A. Afzali-Kusha, M. Nagata, N.K. Verghese, and D.J. Allstot, “Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation,” to appear in Proceedings of the IEEE, Dec. 2006.

16. B. Bornoosh, A. Afzali-Kusha, R. Dehghani, M. Mehrara, S.M. Atarodi, and M. Nourani, “Reduced Complexity 1-Bit High-Order Digital Delta-Sigma Modulator for Low-Voltage Fractional-N Frequency Synthesis Applications,” The IEE-Proceedings Circuits, Devices & Systems, vol. 152, no. 5, October 2005, pp. 471–477.

17. P. Hashemi, A. Behnam, E. Fathi, A. Afzali-Kusha, and M. El Nokali, “2-D Modeling of Potential Distribution and Threshold Voltage of Short Channel Fully Depleted Dual Material Gate SOI MESFET,” Solid-State Electronics, vol. 49, no. 8, pp. 1341–1346, August, 2005.

18. B. Afzal, A. Zahabi, A. Amirabadi, Y. Koolivand, A. Afzali-Kusha, and M. El Nokali, “Analytical Model for C-V Characteristic of Fully-Depleted SOI-MOS Capacitors,” Solid-State Electronics, vol. 49, no. 8, pp. 1262–1273, August, 2005.

19. S.H. Rasouli, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani “Low-power single and double edge-triggered flip-flops for high speed applications,” IEE Proceedings-Circuits, Devices and Systems, vol. 152, no. 2, pp. 118-122, April 2005.

20. D. Shahrjerdi, B. Hekmatshoar, A. Khakifirooz, and A. Afzali-Kusha, “Optimization of the VT-Control Method for Low-Power Ultra-Thin Double-Gate SOI Logic Circuits,” The VLSI Journal of Integration, vol. 38, issue 3, January 2005, pp. 505-513.

21. S. Hatami, M.Y. Azizi, H.R. Bahrami, D. Motavalizadeh, and A. Afzali-Kusha “Accurate and Efficient Modeling of SOI MOSFET with Technology Independent Neural Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 11, pp. 1580-1587, 2004.

22. A. Abbasian, S.H. Rasouli, A. Afzali-Kusha, and M. Nourani “No-race Charge Recycling Complementary Pass transistor Logic (NCRCPL) and its Pipeline Event-driven Structure for Low Power Applications,” IEE Proceedings of Computer and Digital Techniques, vol. 151, no. 3, pp. 183-190, May 2004.

23. S. Bolouki, M. Maddah, A. Afzali-Kusha, and M. El Nokali, “A Unified I-V model for PD/FD SOI MOSFETs with a Compact Model for Floating Body Effects,” Solid-State Electronics, vol. 47, no. 11, pp. 1909-1915, November 2003.

24. H. Mahmoodi-Meimand, A. Afzali-Kusha and M. Nourani, “Adiabatic carry look-ahead adder with efficient power clock generator,” IEE Proceedings-Circuits, Devices and Systems, vol. 148, no. 5, pp. 229-234, 2001.