journal

  • M. Kamal, A. Afzali-Kusha, S. Safari, and M. Pedram, “Considering the Effect of Process Variations during the ISA Extension Design Flow”, Accepted for publication in Microprocessors and Microsystems.

  • B. Afzal, A. Afzali-Kusha, and M. Pedram, “Analytical Modeling of Read Margin Probability Distribution Function of SRAM Cells in Presence of Process Variations and NBTI Effect,” Accepted for publication in Japanese Journal of Applied Physics.

  • S. Mohammadi., A. Afzali-Kusha, and S. Mohammadi, “Performance Improvement of Partially Silicon-on-Insulator Lateral Double-Diffused Metal Oxide Semiconductor Field Effect Transistors Using Doping-Engineered Drift Region,” Accepted for publication in Japanese Journal of Applied Physics.

  • B. Afzal, B. Ebrahimi, A. Afzali-Kusha, and H. Mahmoodi “Modeling read SNM considering both soft oxide breakdown and negative bias temperature instability” Accepted for publication in Microelectronics Reliability.

  • H. Aghababa, A. Khosropour, A. Afzali-Kusha, B. Forouzandeh, and M. Pedram, “Statistical Estimation of Leakage Power Dissipation in Nano-Scale CMOS Digital Circuits using Generalized Extreme Value Distribution,” Accepted for publication in IET Circuits, Devices & Systems.

  • H. Aghababa, B. Ebrahimi, A. Afzali-Kusha, and M. Pedram, “Probability calculation of read failures in nano-scaled SRAM cells under process variations,” Microelectronics Reliability, vol. 52, no. 11, 2012, pp. 2805-2811.

  • B. Afzal, B. Ebrahimi, A. Afzali-Kusha, and S. Mohammadi “Calculation of on-state I–V characteristics of LDMOSFETs based on an accurate LDD resistance modeling,” Superlattices and Microstructures, vol. 52, no. 3, September 2012, pp. 560–576.

  • G. Rostami, M. Shahabadi, A. Afzali Kusha, and A. Rostami, “Nanoscale all-optical plasmonic switching using electromagnetically induced transparency,” Applied Optics, vol. 51, no. 21, July 2012, pp. 5019-5027.

  • M. Tinati, A. Khademzadeh, A. Afzali-Kusha, M. Janidarmian, “HACS: A novel cost aware paradigm promising fault tolerance on mesh-based network on chip architecture,” Computers & Electrical Engineering, vol. 38, no. 4, July 2012, pp. 963-974.

  • M. Saremi, A. Afzali-Kusha, and S. Mohammadi, “Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits”, Microelectronic Engineering, vol. 95, July 2012, pp. 74-82.

  • H. Aghababa, B. Forouzandeh, and A. Afzali-Kusha, “High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility,” Journal of Zhejiang University - Science C, vol. 13, no. 6, June 2012, pp. 460-471.

  • M. Nickray, A. Afzali-Kusha, and R. Jäntti, “MEA: an energy efficient algorithm for dense sector-based wireless sensor networks,” EURASIP Journal on Wireless Communication and Networking, no. 85, March 2012, pp. 1-13.

  • B. Ebrahimi, B. Afzal, A. Afzali-Kusha, and S. Mohammadi “A RESURF LDMOSFET with a dummy gate on partial SOI,” Journal of the Korean Physical Society, vol. 60, no. 5, March 2012, pp. 842-848.

  • M. Daneshtalab, M. Kamali, M. Ebrahimi, S. Mohammadi, A. Afzali-Kusha, and J. Plosila, “Adaptive Input-Output Selection Based On-Chip Router Architecture” Journal of Low Power Electronics, vol. 8, no. 1, February 2012, pp. 11-29.

  • G. Rostami, M. Shahabadi, A. Afzali-Kusha, and A. Rostami, “EIT based tunable metal composite spherical nanoparticles,” Photonics and Nanostructures – Fundamentals and Applications, vol. 10, no. 1,  January 2012, 102–111.

  • B. Afzal. B. Ebrahimi, A. Afzali-Kusha, and M. Pedram, “An accurate analytical I-V odel for sub-90-nm MOSFETs and its application to read SNM modeling,” Journal of Zhejiang University-SCIENCE C (Computer & Electronics), vol. 13, no. 1, January 2012, pp. 58-70.

  • M. Saremi, B. Ebrahimi, A. Afzali-Kusha, and S. Mohammadi “A partial-SOI LDMOSFET with triangular buried-oxide for breakdown voltage improvement” Microelectronics Reliability, vol. 51, no. 12, December 2011, pp. 2069-2076.

  • S. Mohammadi, A. Afzali-Kusha, and S. Mohammadi, “Drain current model for strained-Si/Si1−xGex/strained-Si double-gate MOSFETs including quantum effects,” Semiconductor Science and Technology, vol. 26, no. 9, September 2011, 095022 doi: 10.1088/0268-1242/26/9/095022.

  • H. Aghababa, R. Asadpour, A. Afzali-Kusha, and B. Forouzandeh “Finding optimum value of numerical aperture for the best aerial image quality,” IEICE Electronics Express, December 2011, vol. 8, no. 11, pp. 879–883.

  • M. Rostami, B. Ebrahimi, A. Afzali-Kusha, and M. Pedram, “Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage” IEEE Transactions on Very Large Scale Integrated Circuits, vol. 19, no. 10, October 2011, pp. 1911-1916.

  • M. E. Salehi, M. Samadi, M. Najibi, A. Afzali-Kusha, M. Pedram, S. M. Fakhraie, “Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power and Timing Constraints” IEEE Transactions on Very Large Scale Integrated Circuits, vol. 19, no. 10, October 2011, pp. 1931-1935.

  • P. Lotfi-Kamran, A.-M. Rahmani, A.-A. Salehpour, A. Afzali-Kusha, and Z. Navabi, “Dynamic Power Reduction of Stalls in Pipeline Architecture Processors,” International Journal of Design, Analysis and Tools for Integrated Circuits and Systems, vol. 1, no. 1, pp. 9-15, June 2011.

  • S. Mohammadi, A. Afzali-Kusha, and S. Mohammadi, “Compact Modeling of Short Channel Effects in Symmetric and Asymmetric 3-T/4-T Double Gate MOSFETs” Microelectronics Reliability, vol. 51, no. 3, March. 2011, pp. 543-549

  1. H. R. Ahmadi, A. Afzali-Kusha, and M. Pedram, "A Power-Optimized Low-Energy Elliptic-Curve Crypto-processor”, IEICE Electronics Express, Vol. 7, No. 23, pp.1752-1759, Dec. 2010.

  2. H. R. Ahmadi, and A. Afzali-Kusha, "A Low-Power and Low-Energy Flexible GF(p) ECC Processor," Journal of Zhejiang University - Science C, vol. 11, no. 9, pp. 724-736, Sep 2010.

  3. P. Lotfi-Kamran, A.-M. Rahmani, M. Daneshtalab, A. Afzali-Kusha, and Z. Navabi, “EDXY - A Smart Congestion-Aware and Link Failure Tolerant Routing Algorithm for Network-on-Chips,” Journal of Systems Architecture, vol. 56, no. 7, 2010, pp. 256-264.

  4. E. Rokhsat-Yazdi, A. Afzali-Kusha, and M. Pedram, “A High-Efficiency, Auto Mode-Hop,Variable-Voltage, Ripple Control Buck Converter,” Journal of Power Electronics, vol. 10, no. 2, March 2010, pp. 115-124.

  5. S. Mohammadi and A. Afzali-Kusha, “Modeling of drain current, capacitance and transconductance in thin film undoped symmetric DG MOSFETs including quantum effects,” Microelectronics Reliability, vol. 50, no. 3, March 2010, pp. 338-345.

  6. S. Mohammadi and A. Afzali-Kusha, “An Efficient Quantum-Based Model for the Threshold Voltage of Thin Film Double Gate/Silicon on Insulator Silicon Metal Oxide Semiconductor Field Effect Transistors,” Japanese Journal of Applied Physics, vol. 49, no. 2, March 2010, pp. 024304-024304-8.

  7. A.-M. Rahmani, A. Afzali-Kusha, and M. Pedram, “A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution,” Journal of Low Power Electronics, vol. 5, no. 3, October 2009, pp. 396-405.

  8. A.-M. Rahmani, M. Daneshtalab, A. Afzali-Kusha, and M. Pedram, “Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips,” Journal of Low Power Electronics, vol. 5, no. 3, October 2009, pp. 385-395.

  9. G. Razavipour, A. Afzali-Kusha, and M. Pedram, “Design and Analysis of Two Low Power SRAM Cell Structures,” IEEE Transactions on Very Large Scale Integrated Circuits, vol. 17, no. 10,  Oct. 2009, pp. 1551 – 1555.

  10. M. Daneshtalab, M. Ebrahimi, S. Mohammadi, and A. Afzali-Kusha, “Low-distance Path-based Multicast Routing Algorithm for Network-on-Chips,” IET Proceedings of Computer and Digital Techniques, vol. 3, no. 5,  pp. 430-442, Sept. 2009

  11. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “Sign Bit Reduction Encoding For Low Power Applications,” Journal of VLSI Signal Processing Systems, September 2009, vol. 57, no. 3, pp. 321 – 329.

  12. M. Mottaghi-Dastjerdi, A. Afzali-Kusha, and M. Pedram, “BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture,” IEEE Transactions on Very Large Scale Integrated Circuits, 2009, vol. 17, no. 2, pp. 302 – 306.

  13. M. Saneei, A. Afzali-Kusha, and M. Pedram, “Two High Performance and Low Power Serial Communication Interfaces for On-chip Interconnects,” Canadian Journal of Electrical and Computer Engineering, July 2008.

  14. G. Razavipour, A. Afzali-Kusha, and M. Pedram, “Design and Analysis of Two Low Power SRAM Cell Structures,” IEEE Transactions on Very Large Scale Integrated Circuits, July 2008.

  15. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “A Low-Power High Throughput Link Splitting Router for NoCs,” Journal of Zhejiang University-SCIENCE A, 2008, vol. 9, no. 12, pp. 1708 – 1714.

  16. M. Samadi and A. Afzali-Kusha, “Dynamic power management with fuzzy decision support system,” IEICE Electronics Express, August 2008, vol. 5, no. 19, pp. 789 – 795.

  17. A. Abbasian, S. Hatami, A. Afzali-Kusha, and M. Pedram, "Wavelet-Based Dynamic Power Management for Non-stationary Service Requests," ACM Transactions on Design Automation of Electronic Systems, 2008, vol. 13, no. 1, article 13, pp. 13:1-13:41.

  18. H. Parehdeh-Afshar, M. Saneei, A. Afzali-Kusha, and M. Pedram, "Fast INC-XOR codec for low-power address buses," IET Comput. Digit. Tech., 2007, vol. 1, no. 5, pp. 625-631.

  19.  A. Mehran, S. Saeidi, A. Khademzadeh, and A. Afzali-Kusha, "Spiral: A heuristic mapping algorithm for network on chip," IEICE Electronics Express, 2007, vol. 4, no. 15, August 10, 2007, pp. 478-484.

  20. F. Aezinia and A. Afzali-Kusha, "Low Power High Performance Level Converter for Dual Supply Voltage Systems," IEICE Electronics Express, vol. 4 (2007), no. 9, pp. 306-311.

  21. K. Shoajee, M. Gholipour, A. Afzali-Kusha, and M. Nourani, “Comparative study of asynchronous pipeline design methods”, IEICE Electronics Express, vol. 3, no. 8, April 2006, pp. 163–171.

  22. A. Amirabadi, Y. Mortazavi, A. Afzali-Kusha, and M. Nourani, “Clock Delayed Domino Logic with Efficient Variable Threshold Voltage Keeper,” Accepted for publication in IEEE Transaction on Very Large Scale Integrated Circuits, October 2006.

  23. S. Sharifi, J. Jaffari, M. Hosseinabady, A. Afzali-Kusha, and Z. Navabi, “Scan-Based Structure with Reduced Static and Dynamic Power Consumption,” to appear in Journal of Low Power Electronics, vol. 2, no. 3, Dec. 2006, pp. 477-487.

  24. A. Afzali-Kusha, M. Nagata, N.K. Verghese, and D.J. Allstot, “Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation,” to appear in Proceedings of the IEEE, Dec. 2006.

  25. B. Bornoosh, A. Afzali-Kusha, R. Dehghani, M. Mehrara, S.M. Atarodi, and M. Nourani, “Reduced Complexity 1-Bit High-Order Digital Delta-Sigma Modulator for Low-Voltage Fractional-N Frequency Synthesis Applications,” The IEE-Proceedings Circuits, Devices & Systems, vol. 152, no. 5, October 2005, pp. 471–477.

  26. P. Hashemi, A. Behnam, E. Fathi, A. Afzali-Kusha, and M. El Nokali, “2-D Modeling of Potential Distribution and Threshold Voltage of Short Channel Fully Depleted Dual Material Gate SOI MESFET,” Solid-State Electronics, vol. 49, no. 8, pp. 1341–1346, August, 2005.

  27. B. Afzal, A. Zahabi, A. Amirabadi, Y. Koolivand, A. Afzali-Kusha, and M. El Nokali, “Analytical Model for C-V Characteristic of Fully-Depleted SOI-MOS Capacitors,” Solid-State Electronics, vol. 49, no. 8, pp. 1262–1273, August, 2005.

  28. S.H. Rasouli, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani “Low-power single and double edge-triggered flip-flops for high speed applications,” IEE Proceedings-Circuits, Devices and Systems, vol. 152, no. 2, pp. 118-122, April 2005.

  29. D. Shahrjerdi, B. Hekmatshoar, A. Khakifirooz, and A. Afzali-Kusha, “Optimization of the VT-Control Method for Low-Power Ultra-Thin Double-Gate SOI Logic Circuits,” The VLSI Journal of Integration, vol. 38, issue 3, January 2005, pp. 505-513.

  30. S. Hatami, M.Y. Azizi, H.R. Bahrami, D. Motavalizadeh, and A. Afzali-Kusha “Accurate and Efficient Modeling of SOI MOSFET with Technology Independent Neural Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 11, pp. 1580-1587, 2004.

  31. A. Abbasian, S.H. Rasouli, A. Afzali-Kusha, and M. Nourani “No-race Charge Recycling Complementary Pass transistor Logic (NCRCPL) and its Pipeline Event-driven Structure for Low Power Applications,” IEE Proceedings of Computer and Digital Techniques, vol. 151, no. 3, pp. 183-190, May 2004.

  32. S. Bolouki, M. Maddah, A. Afzali-Kusha, and M. El Nokali, “A Unified I-V model for PD/FD SOI MOSFETs with a Compact Model for Floating Body Effects,” Solid-State Electronics, vol. 47, no. 11, pp. 1909-1915, November 2003.

  33. H. Mahmoodi-Meimand, A. Afzali-Kusha and M. Nourani, “Adiabatic carry look-ahead adder with efficient power clock generator,” IEE Proceedings-Circuits, Devices and Systems, vol. 148, no. 5, pp. 229-234, 2001.