Mohsen Saneei

PhD Student

Electrical and Computer Engineering Department

Faculty of Engineering, University of Tehran

Phone: (+98) 913-341-0024

msaneei@ut.ac.ir

mohsen.saneei@gmail.com

mohsen.saneei@ece.ut.ac.ir

Tel: +98 912 2057994

Personal

• Born in January 1969, Kerman, Iran.

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Education

• Ph.D. Electrical Engineering, Computer Architecture

• University of Tehran, Tehran, Iran, Sept. 2002-Now.

• Major: Digital Design, Minor: Computer Architecture.

• Dissertation title: “Reduction of data transfer power consumption in NoCs”

• M.Sc. Electrical Engineering,

• Iran University of Since and Technology, Tehran, Iran, Sept. 1992-Sept. 1995.

• Major: Circuits.

• Thesis title: “Wide Band and Integrated Amplifier Design”

• B.Sc. Electrical Engineering,

• Sharif University of Technology, Tehran, Iran, Sept. 1987 - Sept 1992.

• Project title: “Design and Implementation of a Digital Planimeter”

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Research Areas/Interest

• Network-on-Chip and System-on-Chip

• Low Power Design

• Digital Design

• Nanotechnology

• FPGA

• Computer Architecture

• Design with HDL

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Publications

             Conference Paper:

1. K. H. Rouintan, M. Saneei, “Distortion Reduction in diffusion Resistors," in Proceedings of 4th Iranian Conference on Electrical Engineering, Tehran, Iran, May 1996.

2. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “A Low Power Technique Based on Sign Bit Reduction,” in Proceedings of the 16Pth P International Conference on Microelectronics (ICM), Tunis, Tunisia, December 6-8, pp. 497-500, 2004.

3. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “Sign Bit Reduction Encoding For Low Power Applications,” in Proceedings of Design Automation Conference (DAC) Anaheim, U.S.A., June 2005.

4. M. Saneei, A. Afzali-Kusha,and  Z. Navabi, “Low-power and Low-latency Cluster Topology for Local Traffic NoCs,”  ISCAS 2006, Kos Island, Greece, May 2006.

5. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “Low-latency Multi-Level Mesh Topology for NoCs,” in Proceedings of the 18th International Conference on Microelectronics, Saudi Arabia, Dec. 17-19, 2006

6. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “A Mesochronous Technique for Communication in Network on Chips,” in Proceedings of the 18th International Conference on Microelectronics, Saudi Arabia, Dec. 17-19, 2006.

7. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “Serial Bus Encoding for Low Power Application,” in Proceedings of the International Symposium on System-on-Chip, Tampere, Finland, Nov. 14-16, 2006, pp. 99-102.

8. Mohammad-Reza Binesh-Marvasti, Mohsen Saneei, and Ali Afzali-Kusha, “Time-Efficient Power-Constrained Core Mapping Algorithm in NoC Based on Genetic Algorithm,” in Proceedings of the 5th  IEEE East-West Design & Test Symposium (EWDTS), Yerevan, September 7-10, 2007, pp. 205-210

                Journal Paper:

1. H. Parandeh-Afshar, M. Saneei, A. Afzali-Kusha, and M. Pedram , “A Fast INC-XOR Codec for Low Power Address Buses,” Journal of IET Computers & Digital Techniques, Vol. 1, No. 5, September 2007, pp. 625-631.

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Skills and Experiences

• Design and implementation a PCI Express IP Core for Endpoint.

• SDH/PDH Networking (STM-1, E1, E3, E4)

• Design and fabricate a Magnetic Separator.

• Design and implementation an EPROM programmer

• EDA Tools: Xilinx ISE, Altera Max Plus II, Altera Quartus II, ModelSim, Leonardo Spectrum, HSPICE

•  Hardware description languages: VHDL, Verilog.

• Programming languages: C/C++, MPI parallel processing library.

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Teaching and Academic Experiences

• COURSES TAUGHT:  

• Microprocessors and Microcontroller

• Computer Architecture

• Electronic Circuits

• Logical Design

• Electrical Circuits

• Pulse Technique Circuits.

• PROFESSIONAL EXPERIENCE:

• Faculty Member of Electronic Engineering Department, Azad University of Kerman, Sept. 1995-Jan. 2004

• Head of Electronic Engineering Department, Azad University of Kerman, March 1998-Dec. 2001

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