Mehrzad Samadi

Mehrzad Samadi

 

m.bahar@ece.ut.ac.ir

Tel: +98 912 1642329

Group: Device and Digital Group

 

Personal

  • Born in April 1983, Tehran, Iran.
  • Married.

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Education

·     University of Tehran, Tehran, Iran

2005 – present

M.S — Electrical and Computer Engineering - Circuits and Systems

Advisor: Prof. Ali Afzali-Kusha

Thesis title: Dynamic power management and voltage/frequency scaling in nano-scale devices

GPA: 19.2/20.0

·     Sharif University of Technology, Tehran, Iran

B.S. — Electrical Engineering

GPA: 16.5/20.0

2001 – 2005

 

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Honors and Awards

·     Ranked 40th in the nationwide university entrance exam for graduate

   studies, Iran

·     Ranked 52th among 350,000 participants in the nationwide university

   entrance exam, Iran

·     Awarded the silver medal in the National Computer Olympiad

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Publications

·      Power Management with Fuzzy Decision Support System

Mehrzad Samadi and Ali Afzali-Kusha

To appear in the IEICE Electronics Express Journal

·      Power Management with Fuzzy Decision Support System

Mehrzad Samadi and Ali Afzali-Kusha

In Proc. of the 7th International conference on ASIC (ASICON’07), pp. 73 - 77,

Oct. 2007

·      Power Management by Brain Emotional Learning Algorithm

Mehrzad Samadi, Ali Afzali-Kusha and Caro Lucas

In Proc. of the 7th International conference on ASIC (ASICON’07), pp. 78 - 81,

Oct. 2007

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Skills

·   Programming languages: Visual C++, MATLAB, Pascal

·   Hardware description languages: VHDL, Verilog

·   EDA Tools: Xilinx ISE, ModelSim, HSPICE

·   SDH/PDH Networking (STM-1, E1, E3, E4)

·   PCB design using Protel DXP

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Work Experiences

·     University of Tehran, Tehran, Iran

Low Power High Performance Nanosystems Lab

Research Assistant

Jan. 2006 – June 2008

·     Pardis Novel Processing Technology Co., Tehran, Iran

March 2006 – present

R&D Engineer

-   Design and FPGA implementation of STM1 radio with low power 16 QAM, 4 QAM, 128 QAMTCM encoder and decoder on a Xilinx Virtex IV FPGA.   

-   Design and implementation of MPEG Transport Stream Analyzer on a Xilinx Virtex IV FPGA.

o    Detect and locate errors in order to keep the quality of service as high as possible.

o    Generate a recorded Transport Stream for any TS-input systems such as modulators and encoders.

o    Web based user interface

-   Design and implementation of a Digital Video Broadcast Transmitter (DVBT/H) on a Xilinx Spartan III FPGA.

o    A high capacity OFDM modulator

o    FFT                            2K,4K,and 8K  

o    Guard Intervals            1/4, 1/8, 1/16, 1/32

o    FEC                            1/2, 2/3, 3/4, 5/6, 7/8

o    Constellations               QPSK, 16QAM, 64QAM

o    Network mode             MFN

o    Inner interleave         Native/ In depth (DVB-H only)

o    Channel Bandwidth        8MHz,7MHz,6MHz,5MHz

o    TPS signal                    DVB-T or DVB-H

-   Design of Fast Ethernet board and implement the TCP/IP layers in VHDL for 10/100/1000 Mbps Ethernet

 

 

·     Sharif University of Technology

B.S project

- Design and development of Image Watermarking algorithms

Jan. 2005  - June 2005

·     Eima Company, Tehran, Iran

June. 2004 – Sept. 2004

Intern

-  Design and development of message transformation in MMS server in linux

 

 

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Teaching Experiences

·     Teaching assistant for computer programming course, Sharif University of Technology

Fall 2002

·     Teaching Pascal Programming to High School Students

2001

·     Teaching Algorithms to High School Students for Computer Olympiad

2001

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Graduate Courses

·   Advance VLSI (University of Tehran, Iran)

·   Low Power Circuits (University of Tehran, Iran)

·   Digital Signal Processing (Sharif University of Technology, Iran)

·   Advanced Digital Communication (Sharif University of Technology, Iran)

·   Integrated Circuit Design (University of Tehran, Iran)

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Language Proficient

  • English: writing and speaking

  • French: writing and speaking

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