Amir-Mohammad Rahmani

M.Sc.

 

am.rahmani@ece.ut.ac.ir

Tel: +98 915 1111 253

Group: Network on Chip and Reconfigurable Computing Group

Personal

  • Born in 1984, Mashhad, Iran.
  • Married Since 2008.

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Education

  • 2006-2009: M.Sc. Degree in Computer Engineering - Computer Architecture, University of Tehran, Tehran, Iran, GPA 3.56/4.
  • 2002-2006: B.Sc. Degree in Hardware Computer Engineering, Engineering Faculty, Azad University of Mashhad, Mashhad, Iran, GPA 3.052/4.
  • 2002: High School Diploma of Physics and Mathematics, Imam Hossein High School, Mashhad, Iran, GPA 3.8/4.

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Honors

  • 2006, Ranked No. 1 in global master exam among all Hardware Computer Engineering students of the Azad University of Mashhad.
  • 2006,  Ranked No. 55 in the entrance exam of the M.Sc. degree (nation-wide).

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Publications 

Journal:

  •     Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, and Masoud Pedram, “Dynamic Power Management for Network-on-Chips Using Exponential Smoothing Forecasting Technique,” Submitted to journal of Electrical Engineering (Springer), 2009.

  •      Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, and Zainalabedin Navabi, “EDXY - A Smart Congestion-Aware and Link Failure Tolerant Routing Algorithm for Network-on-Chips,” Submitted to IET Computers & Digital Techniques Journal, 2009.

  •      Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, and Zainalabedin Navabi, “Dynamic Power Reduction of Stalls in Pipeline Architecture Processors,” Submitted to IEEE Transactions on Computers, 2009.

Conference:

  •      Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Masoud Zamani, Siamak Mohammadi, and Hossein Pedram, “An Efficient Fault Simulator for Template based QDI Asynchronous Circuits,” In Proc. of 4th IEEE Southern Conference on Programmable Logic (SPL’08), pp. 99-104, 2008, Argentina.

  •      Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, and Zainalabedin Navabi, “Stall Power Reduction in Pipelined Architecture Processors,” In Proc. of 21st IEEE International Conference on VLSI Design (VLSID’08), pp. 541,546, 2008, India.

  •      Ali-Asghar Salehpour, Masoud Zamani, Amir-Mohammad Rahmani,  Siamak Mohammadi, and Hossein Pedram, “A Novel Test Environment for Template based QDI Asynchronous Circuits,” In Proc. of 15th IEEE International Conference on Electronics, Circuits, and Systems (ICECS’08), pp. 526-529, 2008, Malta.

  •      Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Saeed Safari, and Masoud Pedram, “Forecasting-based Dynamic Virtual Channels Allocation for Power Optimization of Network-on- Chips,” In Proc. of 22st IEEE International Conference on VLSI Design (VLSID’09), pp. 151-156, 2009, India.

  •      Amir-Mohammad Rahmani, Iman Kamali, Pejman Lotfi-Kamran, Ali Afzali-Kusha, and Saeed Safari, “Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips,” In Proc. of 22st IEEE International Conference on VLSI Design (VLSID’09), pp. 157-162, 2009, India.

  •      Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, and Saeed Safari, “Power Efficient Switches with Dynamic Virtual Channel Allocation for Network-on-Chips,” In Proc. of 5th International Conference on Innovations in Information Technology(Innovations’08), pp. 121-125, 2008, UAE.      

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Skills and Experiences

-Hardware-Based

  • Extensive experience in VHDL, Verilog and SystemC HDL-based hardware design (both for modeling and synthesis)

  • Experience in HDL-based modeling of systems

  • Extensive experience in the area of FPGA-based and microcontroller-based hardware implementation

  • Experience in digital hardware power analysis and optimization for special applications

  • Experience in functional verification of HDL-based hardware design with below languages :

    • OVL

    • PSL

    • PLI

    • SystemC

  • Experience in digital ASIC synthesis

  • Experience in test of digital circuits

  • Experience in asynchronous digital design with below languages :

    • PERSIA

    • PETRIFY

    • BALSA

  • Experience in many CAD and simulation tools:

    • "Active HDL", "Modelsim", "Leonardo Spectrum", " Xilinx ISE", "Quartus", "PSPICE", "HSPISE", "SYNOPSYS Design Analyzer", "Synplify", "Matlab", "CodeVision", etc.

-Software-Based

  • Extensive experience in C/C++, Pascal, Fortran Programming and assembly code developing

  • Extensive Experience in Windows and Web Programming Based on .Net Framework 1.0 and 2.0 with blow languages:

    • VB.NET

    • C#.NET

    • ASP.NET

  • Extensive Experience in Database Management and Programming based on Microsoft SQL Server

  • Extensive Experience in Security in Web Applications

  • Experience in Network Administration based on Windows Server platform

  • Experience in below JAVA Technologies:

    • J2SE

    • J2EE

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Research Interest

  • Low Power Design

  • Network-on-Chips and System-on-Chips

  • Digital Design

  • Nanotechnology

  • FPGA and ASIC

  • Processor Design

  • Computer Architecture

  • Power/Performance Analysis

  • Routing Alogorithm

  • Low Power Cryptography

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