Mohsen Jafari

M.Sc. Graduated

 

mohsen_jafari [AT] ut.ac.ir

Group: VLSI Device and Circuits

Thesis Title: Digital Circuits Design in Near-threshold Region Considering Process Variation

Personal

  • Born in Feb 1989, Tehran, Iran.
  • Single.

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Education

  • 2011 - Present: M.Sc. Degree in Electrical and Electronics Engineering, University of Tehran, Tehran, Iran, GPA 19.46/20 (1st Rank Student), Thesis: Digital Circuits Design in Near-threshold Region Considering Process Variation (Advisor: Dr. Afzali-Kusha)
  • 2007 - 2011: B.Sc. Degree in Electrical and Electronics Engineering, University of Tehran, Tehran, Iran, GPA 17.44/20, Project: CV measurement for MOS and semiconductor contact(Advisor: Dr. Fathipour)
  • 2008 - 2011: Double B.Sc. Degree in Business Management, University of Tehran, Tehran, Iran, GPA 16.69/20,
  • 2003-2007: High School Diploma of Physics and Mathematics, Seyed Alshohada Education Center Tehran, Iran GPA 19.97/20

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Research Interests

  • Nano-scaled transistors (including FinFET, strained channel transistors) current-voltage characteristics investigation and modeling
  • Low-Power High-Performance Circuits/Architectures/Systems.
  • Process variation tolerant design for nano-scaled VLSI device and circuits
  • Near/sub threshold region
  • MEMS structures
  • Biomedical Engineering.

Honors

      • 2011-2013, 1st Rank among all Electronic-circuit and system Students.
      • 2006, Ranked No. 140 in the university entrance exams (nation-wide) among more than 400,000.
      • 2008, Pursuing Business management simultaneously as second field of study available for exceptional students of University of Tehran.
      • 2011, Accepted without entrance exam (straight) for M.Sc. degree for being among top 10% student.

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Publications

IEEE International Conference Papers

    Jafari, M., Imani, M., Ansari, M., Fathipour, M., & Sehatbakhsh, "Design of an Ultra-Low Power 32-bit Adder Operating at Subthreshold Voltages in 45-nm FinFET.", 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, Dubai, 2013.

    Jafari, M., Imani, M., Fathipour, M., & Sehatbakhsh. " Bottom-up design of a high performance ultra-low power DFT utilizing multiple-VDD, multiple-Vth and gate sizing.", 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Dubai, IEEE, 2013.

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Skills and Experiences

In depth practical experience with application such as:

  • Electronic Design Automation Tools: ModelSim, Quartus, ISE-Xilinx, HSPICE(Expert), ADS,Matlab/Simulink(Expert), Labview, Altium Designer, Proteus and DC shell.

  • Device design Tools: Solid works, Intelisuit, Comsol, Silvaco. (Expert)

  • Software Programming language:C,C++(Expert),G++,Java(familiar), Assembly Language

  • Hardware Programming language: System C,Verilog, VHDL(both for modeling and synthesis). (Expert)

       OS and others: Win98,XP,2000,Vista,se7en,Linux, Mac, Office(Expert)

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Work Experiences

    Summer 2009 : Digital Design Lab., School of ECE, University of Tehran, Iran.

    •  Preparing Instruction papers for Lab, and devising a new set of experiments for this lab.

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