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Group: Network on Chip and Reconfigurable Computing
Thesis Title: Design, Implementation, and Evaluation of
topologies and protocols in Network on Chip (NoC)
Personal
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Born in Sep 1980, Sirjan,
Iran.
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Education
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University of Tehran Tehran-Iran
- Compute
System Architecture 2003-2006
- Thesis: Design,
Implementation, and Evaluation of topologies and
protocols in Network on chip (NoC)
- Advisors: Prof. Ali
Afzali-Kusha, Prof. Zainalabedin Navabi
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GPA 18.56 out of 20.00
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Iran
Univ. of Science and Technology
Tehran, Iran
- B.Sc.
Hardware
Engineering
1998 –2002
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Thesis: Implementation a Minesweeper Robot.
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Advisors: Prof. Naser Mozayeni
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GPA 17.10 out of 20.00
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Mostafa
Khomeni High School
Sirjan, Iran
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Diploma, Physics and Mathematics
1994 –1998
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GPA 18.85 out of 20.00
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Honors
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Ranked first among
computer engineering under graduated students of the
2002 class.
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Awarded the rank first
prize of the Department of Computer Engineering
in 2002.
- ●
Awarded the rank first
prize of the Department of Computer Engineering
in 2001.
- ●
Awarded the rank first
prize of the Department of Computer Engineering
in 1999.
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Publications
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M. Dehyadgari,
M. Nickray, A. Afzali-kusha, Z. Navabi, “A New Protocol
stack Model for Network on Chip,” Emerging VLSI
Technologies and 2006. IEEE Computer Society Annual
Symposium on, Volume 00, 02-03 March 2006
Page(s):440 – 441.
●
M. Dehyadgari, M. Nickray, A. Afzali-kusha, Z. Navabi, “Evaluation of Pseudo
Adaptive XY Routing Using an Object Oriented Model for
NOC” The17th International Conference on
Microelectronics.13-15 Dec. 2005 Page(s):204- 208
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M. Dehyadgari,
M. Nickray, A. Afzali-kusha, “Low Power Communication
for Network on Chip” International Symposium on
Telecommunications, 10-12 Sep. 2005.
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M. R. Jamali, M.
Valadbeigi, M. Dehyadegari, Z. Navabi and C.
Lucas, “Toward Embedded Emotionally Intelligent System,
5th IEEE EAST-WEST DESIGN & TEST INTERNATIONAL
SYMPOSIUM, pp. 51-56, 7-10, September 2007.
●
M. Nickray, M.
Dehyadgari, A. Sobhani, A.Afzali-kusha, “ LPPM: Low
Power Partitioned Multiplier” The 17th Iranian
Conference on ElectricalEngineering,13-15 May. 2005.
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M. Nickray, M.
Dehyadgari, A. Afzali-kusha, “Power and delay
optimization for network-on-chip,” Proceedings of the
2005 European Conference on Circuit Theory and
Design.Volume 3, 28 Aug.-2 Sept. 2005 Page(s):III/273
- III/276 vol. 3.
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M. Nickray, M.
Dehyadgari, A. Sobhani, A.Afzali-kusha, “Multiplier
for Correlative Input Patterns” The 17th
International Conference on Microelectronics,13-15
Dec. 2005 Page(s):72 – 74.
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Research Experiences
University
of Tehran, Low power High Performance Nano-system
Laboratory Tehran-Iran
Advisor Prof. Afzali-Kusha Jan. 2004-present
- ● Designed and implemented a NoC
Environment.
- ● Designed a
protocol stack model for Network on Chip.
- ● Developed an
algorithm for mapping application to Network on Chip.
- ● Developed an
algorithm for routing packets in Network on Chip.
- ● Designed a tool
for logic simulation, fault simulation, and fault
generation Gate-level Verilog.
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Iran Univ. of Sci.
& Tech., Project Lab
Tehran-Iran
- Advisors: Prof. Naser
Mozayeni
Jan. 2002-Sep. 2002
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- ● Designed and implemented a
Minesweeper Robot.
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Work Experiences
University of
Tehran, Low power High Performance Nano-system
Laboratory Tehran-Iran
Advisor Prof.
Afzali-Kusha
Jan. 2004-Sep. 2006
- ● As an R&D
designer, designed and implemented an IP-Core for PCIe
End Point.
- ● Tested and
Evaluated Data Link Layer of PCIe.
- ● PCIe Proposal,
“Design and Implementation an IP-Core for PCIe End
Point.
Teaching and Academic Experiences
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Logic Design and
FPGA Lab Univ. of Tehran Jan 2007-Date.
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Circuit Lab Univ. of Tehran Fall. 2005.
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