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Group:
Network on Chip and Reconfigurable Computing Group
Thesis Title:
Improving the low power Methods in Network on Chips for
Nanotechnologies
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Personal
Born in May 1979, Kerman, Iran.
Married.
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Education
2008-Present:
PHD
student, Computer Systems, Faculty of Mathematics and
Natural Sciences, University of TURKU, Finland.
2004-2006: MS student, Computer Hardware
Engineering, Faculty of Engineering, University of
Tehran, Tehran, Iran, Total GPA 18/20.00 (3.6/4).
1998-2002: BS student, Computer Hardware
Engineering, Shahid Bahonar University, Kerman, Iran,
Total GPA 16.16/20.00(3.2/4).
1994-1998: High School Diploma, Boo-ali High School, Tehran, Iran, Total
GPA 16.00/20.00.
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Publications
Book:
Data Structure, Getting ready for MS entrance
exam, 2006, Ghalamchi, ISBN: 964-8180-57-2
Computer Architecture, Getting ready for MS
entrance exam, 2006, Ghalamchi, ISBN: 964-8180-93-8
Digital Design, Getting ready for MS entrance
exam, 2006, Ghalamchi, ISBN: 964-509-153-0
Operating System, Getting ready for MS entrance
exam, 2006, Ghalamchi, ISBN: 964-8180-87-3
Automata, Getting ready for MS entrance exam,
2006, Ghalamchi, ISBN: 964-509-8180-23
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Journal:
M.H Neishaburi,
Mohammad Reza Kakoee, M. Daneshtalab, and
Saeed Safari, "HW/SW
Architecture for Soft-Error Cancellation in
Real-Time Operating System", appeared in
IEICE Electronics
Express ISSN: 1349-2543.
M.
Daneshtalab,
M. Ebrahimi, S. Mohammadi, A. Afzali-Kusha, "Low
distance path-based multicast algorithm in NOCs",
Accepted as minor revision in
IET.
P. Lotfi-Kamran,
M. Daneshtalab,
A. Rahmani, A.
A. Kusha, and Z. Navabi, “EDXY – A Smart
Congestion-Aware and Link Failure Tolerant Routing
Algorithm for Network-on-Chips,” Submitted to
IET.
A. Rahmani,
M.
Daneshtalab, A. A. Kusha, M. Pedram, “Power
Efficient Switches with Dynamic Virtual Channel
Allocation for Network-on-Chips,” will be Submitted
to
JZUS.
Conference:
--
2009 --
[23] M.
Ebrahimi,
M.
Daneshtalab,
S. Mohammadi, A. Afzali-Kusha, H. Tenhunen,
"An
Efficent Dynamic Multicast Routing Protocol for
Distributing Traffic in NOCs", in Proceedings of 12th DATE,
IEEE
Press, pp. , April 2009, France.
[22]
A. M. Rahmani, M. Daneshtalab, A. Afzali-Kusha,
“Forecasting-based Dynamic Virtual Channels
Allocation for Power Optimization of Network-on-
Chips,” in Proceedings of 22th VLSID,
IEEE
Press, pp. , Jan 2009, India.
-- 2008 --
[21]
P.
Lotfi-Kamran, M. Daneshtalab, Z. Navabi, and
C. Lucas, “BARP- A Dynamic Routing Protocol for
Balanced Distribution of Traffic in NoCs to Avoid
Congestion”, in Proceedings of 11th DATE,
IEEE
Press, pp. 1408-1413,
Mar 2008, Germany.
[20] A. M. Rahmani,
Masoud Daneshtalab, Ali Afzali-Kusha, and
Saeed Safari, “Power Efficient Switches with Dynamic
Virtual Channel Allocation for Network-on-Chips,” in
Proceedings of 5th Innovations, IEEE
Press, pp. , Dec 2009, UAE.
[19] B. Marvasti,
M. Daneshtalab, A. Afzali-Kusha, S. Mohammadi, "PAMPR:
Power-Aware and Minimum Path Routing Algorithm for
NoCs",
in Proceedings of
15th
ICECS,
IEEE Press, Sep 2008, Malta.
-- 2007 --
[18] M.
Daneshtalab, A. Afzali-Kusha, S. Mohammadi, "Distributing
Congestions in NoCs through a Dynamic Routing
Algorithm based on Input and Output Selections",
in Proceedings of
20th
VLSID,
IEEE Press,
pp. 546-550,
Jan 2007, India.
[17]
M.H Neishaburi, M. R. Kakoee, M. Daneshtalab,
"On-Chip
Verification of NoCs Using Assertion Processor", DSD (EuroMicro),
IEEE
Press, pp. 535-538,
Aug 2007, Germany.
[16]
M.H Neishaburi, M. R. Kakoee, M. Daneshtalab,
S. Safari, Z. Navabi, "A HW/SW Architecture to
Reduce the Effects of Soft-Errors in Real-Time
Operating System Services",
DDECS,
IEEE Press, pp.1 - 4,
Apr 2007, Poland.
[15]
M.H Neishaburi, M. Daneshtalab, M. R.
Kakoee, S. Safari, "Improving
Robustness of Real-Time Operating Systems (RTOS)
Services Related to Soft-Errors",
AICCSA, IEEE Press,
pp. 528-534,
May 2007, Jordan.
[14]
M.H Neishaburi, M. Daneshtalab, M. Nabi, S.
Mohammadi, "System
Level Voltage Scheduling Technique Using UML-RT
Model", AICCSA,
IEEE Press,
pp. 500-505,
May 2007, Jordan.
-- 2006 --
[13] M.
Daneshtalab, A. Sobhani, M. D. Mottaghi, A.
Afzali-Kusha, O. Fatemi, and Z. Navabi, "Ant Colony
Based Routing Architecture for Minimizing HotSpots
in NOCs", in Proceedings of 19th
SBCCI
, ACM Press, pp. 56 - 61,
Sep 2006, Brazil.
[12] M.
Daneshtalab, A. Sobhani, A. Afzali-Kusha, O.
Fatemi, and Z. Navabi, "NoC Hot Spot minimization
Using AntNet Dynamic Routing Algorithm ",
in Proceedings of
17th
ASAP,
IEEE Press,
pp. 33-38, Sep 2006,
USA.
[11] A. Sobhani, M. Daneshtalab, A. Afzali-Kusha, O. Fatemi, and
Z. Navabi, "Dynamic Routing Algorithm for Avoiding
HotSpots in On-chip Networks",
in Proceedings of
DTIS,
IEEE Press,
pp. 179-183, Sep
2006, Tunis.
[10]
A. Pedram, M. Daneshtalab, and S. M. Fakhraie,
"An Efficient Parallel Architecture for Matrix
Computations", in Proceeding of
Norchip,
IEEE Press, pp. 171-174,
Nov 2006, Sweden.
[9] M. Daneshtalab,
A. Afzali-Kusha, S. Mohammadi, O. Fatemi,
"Minimizing Hot Spots in NoCs through a Dynamic
Routing Algorithm based on Input and Output
Selections", in
Proceedings of 8th SOC,
IEEE Press,
pp. 1-4, Nov 2006,
Finland.
[8] M. Daneshtalab,
A. Pedram, A. Afzali-Kusha, S. Mohammadi, "A New
Fair Dynamic Routing Algorithm for Avoiding Hot
Spots in NoCs", in
Proceedings of ISCIT, IEEE Press, pp.
237-241,
Oct 2006, Thailand.
[7] A. Pedram,
M.
Daneshtalab, N. Sedaghati, and S. M. Fakhraie,
"A High-Performance Memory-Efficient Parallel
Hardware for Matrix Computation in Signal Processing
Applications", in
Proceedings of ISCIT, IEEE Press, pp.
473-478,
Oct 2006, Thailand.
[6] M. D. Mottaghi,
A. Naghilou, M. Daneshtalab, A. Afzali-Kusha,
and Z. Navabi, "Hot Block Ring Counter: A Low Power
Synchronous Ring Counter", ICM,
IEEE Press, pp.
58 - 62,
Dec 2006,
Saudi Arabia.
[5] M. D. Mottaghi,
M. Riazati, M. Daneshtalab, "Finding low
activity op-code sets using genetic computing",
ICM, IEEE Press, pp. 52-57,
Dec
2006, Saudi
Arabia.
[4] M.H.Neishaburi,
M.Hamzeh, M. Daneshtalab, "Voltage
Scheduling Technique during System Level Design
Using UML-RT Model",
IDT,
Nov 2006, Dubai.
[3]
M.H Neishaburi, M. R. Kakoee, M. Daneshtalab,
S. Mohammadi, "Novel Approach for System Level
Voltage Scheduling Technique",
ICEE,
May 2006, Iran.
[2]
M.H Neishaburi, M. R. Kakoee, M. Daneshtalab,
"Assertion
Based Design Error Diagnosis for Core-Based SoCs",
SoCC, Sep 2007, Taiwan.
[1] M. Daneshtalab,
A. Niknafs, “Priority Link State OSPF routing
algorithm” , NCC,
Oct 2002, Iran.
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Research Areas/Interest
Network-on-Chip and
System-on-Chip
Low Power Design
Digital Design
Nanotechnology
FPGA
Computer Architecture
Design with HDL
Embedded OS (RTOS)
Routing Algorithm
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Work Experience
Winter
2005 - Present:
Research assistant in the Low-Power High-Performance
Nano Sytems Laboratory under the supervision of Prof. Ali Afzali-Kusha in University of Tehran. I worked on improving
the low-power methods in Network on Chip.
Network On Chip power
performance Simulation platform with C++ under Linux
OS.
Design a router’s architecture in NoC with systemC
(under Unix) and VHDL.
Thorough study on Network On Chip, Asynchronous
architecture and RTOS.
Spring
2005 - Fall 2005:
Teaching
Circuit Logic, Computer Architecture and Electronic
Digital for students how getting ready for MS
entrance exam, Ghalamchi.
Summer
2004 - Spring 2005:
Security Groups,
Kishware Co., Tehran/Iran. Linux Programming
(C/C++): Developed a
sms-center based on Client/Server.
Fall
2003 - Summer 2004:
Teacher assistant of
logic circuits, computer architecture, Algorithm
Design in computer department of
University of Kerman.
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Professional Experiences
Theoretical background in Neural
Networks, Genetic Algorithm and Ant colony
algorithm.
Software Programming : C/C++
,Pascal, Basic, Fortran.
Script programming : PHP, Perl.
Hardware Programming :
VHDL, Verilog ,SystemC and Balsa (Asynchron
Description Language).
Operating System: Windows,
Linux(In depth practical experience).
Application packages: Modelsim,
ISE, EDK, Kdevelop, Leonardo and Matlab.
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