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Group: Circuit and logic
Thesis Title: Low Power and leakage reduction in VLSI design
in Sub-100 Nanometer Technologies
Personal
- I have got my Master
degree and also my Bachelor degree in electronics
Engineering field from Tehran University. My recent
research includes new methods of power and leakage
reduction in digital circuit especially in sub-100
nanometer technologies.
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Education
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2004-2006: MS student,
Electrical Engineering, Faculty of Engineering,
University of Tehran, Tehran, Iran, Total GPA
17.71/20.00.
- 1999-2003: BS student,
Electrical Engineering, Faculty of Engineering,
University of Tehran, Tehran, Iran, Total GPA
16.13/20.00.
- 1998-1999:
Pre-university Certificate, Farzanegan pre-university
Institute, A division of NODET (National Organization
for Development of Exceptional Talents), Sari, Iran,
Total GPA 19.22/20.00.
- 1996-1999: High School
Diploma, Farzanegan High School, A division of NODET,
Sari, Iran, Total GPA 19.64/20.00.
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Thesis
-
M.Sc. Thesis:
“Low Power and leakage reduction in VLSI design in
Sub-100 Nanometer Technologies” September 2005-September
2006. Advisor: Prof. Ali Afzali-Kusha.
-
B.Sc. Thesis:
“searching on current mode design for mathematic
applications” September 2002-June 2002. Advisor: Prof.
Behjat Forouzandeh.
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Publications
1-
Fatemeh Aezinia,
Ali Afzali-Kusha,
“Low power high performance level converter for dual supply
voltage systems”, IEICE Electron. Express, Vol. 4, No. 9,
pp.306-311, 2007.
2-
Fatemeh Aezinia, Ali Afzali-Kusha, “High Performance
Low Power Level Converter for Dual Supply Systems”, accepted
in International Conference on Microelectronics (ICM), Dec
2006.
3-
Fatemeh Aezinia, and Behjat Frouzandeh, “A Novel Low
Power NOR Gate in SOI CMOS Technology”, Proceedings of the
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Dec 2006.
4-
Fatemeh
Aezinia, Sara Najafzadeh, and Ali Afzali-Kusha, “Novel
High Speed and Low Power Single and Double Edge-Triggered
Flip-Flops”, Proceedings of the IEEE Asia Pacific Conference
on Circuits and Systems (APCCAS), Dec 2006.
5- Fatemeh
Aezinia, Ali Afzali-Kusha, and Caro Lucas, “Optimizing
High Speed Flip-Flop with Genetic Algorithm”, Proceedings of
the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Dec 2006.
6-
Bahman Kheradmand-Boroujeni, Fatemeh Aezinia, and Ali
Afzali-Kusha, “High Performance Circuit Techniques for
Dynamic OR Gates”, Proceedings of the IEEE International
Symposium on Circuits and Systems (ISCAS 2006), May 2006.
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Comleted Projects
-
Spring 2005, Research on Analytical Model for C-V
Characteristic of Fully- Depleted SOI-MOSFET Capacitors,
under supervision of Prof. A. Afzali- Kusha
-
Fall
2005, Research on characteristics of
High-permittivity Materials for DRAM under the
supervision of Prof. A. Afzali-Kusha
-
Winter 2006, Research
on Genetic Algorithm method for Optimization of high
speed flip-flops under the supervision of Prof. C. Lucas
-
Winter 2006, Research on challenges of SOI Circuit
Design especially on SOI NOR gate under the supervision
of Prof. B. Forouzandeh
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Research Interests
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Low
power/low voltage circuit designs
-
Micro
and Nano electronics designs
-
SOI devices and their
application. (fully depleted/partially depleted)
-
Computer architecture for
low power design
-
System
on chip design
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Professional Experiences
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Acquaintance with the theory of power optimization and
Genetic Algorithms.
-
Extensive Experience in project handling with
application packages such as:
-
Analog Circuit
Simulators: HSpice, PSpice
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Digital Circuit
Simulators: Modelsim, QuartezII, Leonardo
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Mathematics Softwares:
Matlab
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Programming: C++, Pascal, Visual C++.
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