Conference

  1. S. Mohammdi and A. Afzali-Kusha, “A Surface Field Based Model for Ultra Thin Body Undoped Symmetric DG MOSFETs,” in Proceedings of Ultimate Integration on Silicon Conference, Aachen, Germany, March 16 – 18, 2009.

  2. N. Ghobadi, A. Afzali-Kusha, and E. Asl-Soleimani, “Modeling Effect of Negative Bias Temperature Instability on Potential Distribution and Degradation of Double-gate MOSFETs,” in Proceedings of Ultimate Integration on Silicon Conference, Aachen, Germany, March 16 – 18, 2009.

  3. N. Ghobadi, A. Afzali-Kusha, and E. Asl-Soleimani, “Analytical Modeling of Negative Bias Temperature Instability in Triple Gate MOSFETs,” in Proceedings of Ultimate Integration on Silicon Conference, Aachen, Germany, March 16 – 18, 2009.

  4. S. Zeinolabedinzadeh, B. Ebrahimi, and A. Afzali-Kusha, “Vth-Control Method in Double Gate Field Effect Transistor Domino Circuits,” in Proceedings of Ultimate Integration on Silicon Conference, Aachen, Germany, March 16 – 18, 2009.

  5. B. Ebrahimi and A. Afzali-Kusha, “NBTI Tolerant 4T Double-Gate SRAM Design,” in Proceedings of Ultimate Integration on Silicon Conference, Aachen, Germany, March 16 – 18, 2009.

  6. B. Bozorgzadeh and A. Afzali-Kusha, “Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies,” in Proceedings of International Conference on VLSI Design, Jan. 5 – 9, 2009, New Delhi, India, pp. 175-180.

  7. A.-M. Rahmani, I. Kamali, P. Lotfi-Kamran, A. Afzali-Kusha, S. Safari, “Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips,” in Proceedings of International Conference on VLSI Design, Jan. 5 – 9, 2009, New Delhi, India, pp. 157-162.

  8. A.-M. Rahmani, M. Daneshtalab, A. Afzali-Kusha, S. Safari, M. Pedram, “Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips,” in Proceedings of International Conference on VLSI Design, Jan. 5 – 9, 2009, New Delhi, India, pp. 151-156.

  9. H.-R. Ahmadi and A. Afzali-Kusha, “Low-Power Flexible GF(p) Elliptic-Curve Cryptography Processor” in Proceedings of 3rd International Design and Test Workshop, Monastir, Tunisia on Dec. 20-22, 2008, pp. 182-186.

  10. A.-M. Rahmani, M. Daneshtalab, A. Afzali-Kusha, and S. Safari “Power Efficient Switches with Dynamic Virtual Channel Allocation for Network-on-Chips,” in Proceedings of the 5th International Conference on Innovations in Information Technology, Dubai, UAE, December 16-18, 2008.

  11. A.-A. Salehpour, B. Mirmobin, A. Afzali-Kusha, and S. Mohammadi, “An Energy Efficient Routing Protocol for Cluster-Based Wireless Sensor Networks Using Ant Colony Optimization,” in Proceedings of the 5th International Conference on Innovations in Information Technology, Dubai, UAE, December 16-18, 2008.

  12. A.-A. Salehpour, A. Afzali-Kusha, and S. Mohammadi, “Efficient Clustering of Wireless Sensor Networks Based on Memetic Algorithm,” in Proceedings of the 5th International Conference on Innovations in Information Technology, Dubai, UAE, December 16-18, 2008.

  13. S. Soleimani, A. Afzali-Kusha, and B. Forouzandeh, “Temperature Dependence of Propagation Delay Characteristic in FinFET Circuits,” in Proceedings of the 20th International Conference on Microelectronics, Sharjah, UAE, Dec. 14-16, 2008, pp. 247-250.

  14. B. Bozorgzadeh, E. Zhian-Tabasi, and A. Afzali-Kusha, “Low-Power High-Performance Logic Style for Low-Voltage CMOS Technologies,” in Proceedings of the 20th International Conference on Microelectronics, Sharjah, UAE, Dec. 14-16, 2008, pp. 251-254.

  15. B. Bozorgzadeh and A. Afzali-Kusha, “Decoupling Capacitor Optimization for Nanotechnology Designs,” in Proceedings of the 20th International Conference on Microelectronics, Sharjah, UAE, Dec. 14-16, 2008, pp. 64-67.

  16. H. Hosseinzadegan, H. Aghababa, M. Zangeneh, A. Afzali-Kusha, and B. Forouzandeh, “A compact current-voltage model for carbon nanotube field effect transistors,” in Proceedings of International Semiconductor Conference, Oct. 13 – 15, 2008, Sinaia, Romania, pp. 359 – 362.

  17. M. Gholipour, A. Afzali-Kusha, and M. Nourani, “A Novel Low Latency Asynchronous Pipeline Control Circuit,” in Proceedings of International Conference on Applied Electronics, Sept. 10 – 11, 2008, Pilsen, Czech Republic, pp. 53-55.

  18. M.-R. Binesh-Marvasti, M. Daneshtalab, A. Afzali-Kusha, and S. Mohammadi, “PAMPR: Power-Aware and Minimum Path Routing Algorithm for NoCs,” in Proceedings of International Conference on Electronics, Circuits, and Systems, Aug. 31 – Sept. 3, 2008, Malta, pp. 418 – 421.

  19. M. Hosseini, A. Jahanshahi, A. Afzali-Kusha, and B. Forouzandeh, “Modeling of Internal and External Fringe Capacitance Poly and Metal Gates in Nanoscale SOI CMOS Devices and Their Variations with Dielectric Constant,” in Proceedings of 16th Iranian Conference on Electrical Engineering, Tehran, Iran, May 14-16, 2008, pp. 6-12.

  20. M. Rostami, B. Ebrahimi, and A. Afzali-Kusha, “Design Centering Scheme for Robust SRAM Cell Design,” in Proceedings of International Conference on Computer and Communication Engineering, May 13-15, 2008, Kuala Lumpur, Malaysia, pp. 871 – 877.

  21. B. Afzal, M. Rostami, M. Samadi, and A. Afzali-Kusha, “An Analytical Model for Threshold Voltage of FinFETs,” in Proceedings of International Conference on Computer and Communication Engineering, May 13-15, 2008, Kuala Lumpur, Malaysia, pp. 760 – 763.

  22. H. Aghababa, M.H.A. Yazdinejad, A. Afzali-Kusha, and B. Forouzandeh, “Simplified Quantum-dot Cellular Automata Implementation of Counters,” in Proceedings of 7th International Caribbean Conference on Devices, Circuits and Systems, Cancun, Mexico, April 28-30, 2008.

  23. H. Aghababa, N. Masoumi, A. Afzali-Kusha, and B. Forouzandeh, “Time-Domain Analysis of Carbon Nanotubes,” in Proceedings of 7th International Caribbean Conference on Devices, Circuits and Systems, Cancun, Mexico, April 28-30, 2008.

  24. H. Aghababa, M. Jourabchian, A. Afzali-Kusha, and B. Forouzandeh, “Asynchronous circuits design using quantum-dot cellular automata for molecular computing,” in Proceedings of 7th International Caribbean Conference on Devices, Circuits, and Systems, Cancun, Mexico, April 28-30, 2008.

  25. B. Ebrahimi, S. Zeinolabedinzadeh, and A. Afzali-Kusha, “Low Standby Power and Robust FinFET Based SRAM Design,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, April 7 – 9, 2008, Montpellier, France, pp. 185-190.

  26. H. Aghababa, M. Jourabchian, B. Forouzandeh, and A. Afzali-Kusha, “Asynchronous Circuits Design Using Quantum-dot Cellular Automata for Molecular Computing,” in Proceedings of Mosharaka International Conference on Communications, Propagation, and Electronics, March 6-8, 2008, Amman, Jordan.

  1. P. Lotfi, A.-M. Rahmani, A.-A. Salehpour, A. Afzali-Kusha, and Z. Navabi “Stall Power Reduction in Pipelined Architecture Processors,” Accepted for presentation at 21st International Conference on VLSI, Hyderabad, January 4-8, 2008.

  2. M. Samadi and A. Afzali-Kusha, “Power Management with Fuzzy Decision Support System,” in Proceedings of The 7th International Conference on ASIC, October 26-29, 2007, Guilin, China.

  3. M. Samadi, A. Afzali-Kusha, and C. Lucas, “Power Management by Brain Emotional Learning Algorithm,” in Proceedings of The 7th International Conference on ASIC, October 26-29, 2007, Guilin, China.

  4. M. A. Karami, M. Ahmadi-Boroujeni, A. Afzali-Kusha, and R. Faraji-Dana, “Semi-Analytic Model for Dispersion Relation of Nanowire Lasers,” in Proceedings of The 2nd International Conference on Nano-Networks, September 24-26, 2007, Catania, Italy.

  5. M.-R. Binesh-Marvasti, M. Saneei, and A. Afzali-Kusha, “Time-Efficient Power-Constrained Core Mapping Algorithm in NoC Based on Genetic Algorithm,” in Proceedings of the IEEE East-West Design & Test International Symposium, September 7-10, 2007, Yerevan, Armenia, pp. 205-210.

  6. M.-R. Binesh-Marvasti, S. Safari, A. Afzali-Kusha, and S. Mohammadi, “A Novel Fault-Tolerant Reconfigurable NoC Architecture,” in Proceedings of the IEEE East-West Design & Test International Symposium, September 7-10, 2007, Yerevan, Armenia, pp. 682-686.

  7. B. Eghbalkhah, B. Afzal, and A. Afzali-Kusha, “Speed Improvement Algorithm for 16×16 Multipliers using Sizing Optimization,” in Proceedings of IEEE International Conference on Design & Technology of Integrated Systems, Rabat, Morocco, September 2-5, 2007, pp. 102-105.

  8. B. Eghbalkhah, B. Bornoosh, Z. Amini-Sheshdeh, and A. Afzali-Kusha, “A New Preamble-less Timing Synchronization Method for OFDM Systems under Multi-Path Channels,” in Proceedings of IEEE International Conference on Design & Technology of Integrated Systems, Rabat, Morocco, September 2-5, 2007, pp. 204-207.

  9. V. Moallemi and A. Afzali-Kusha, “Subthreshold Pass Transistor Logic for Ultra-Low Power Operation,” in Proceedings of 15th Iranian Conference on Electrical Engineering (Electronics), May 15-17, 2007, Tehran, Iran, pp. 138-143.

  10. Z. Jeddi, E. Amini, A. Afzali-Kusha, “Power-Driven Partitioning,” in Proceedings of 15th Iranian Conference on Electrical Engineering (Computer), May 15-17, 2007, Tehran, Iran, pp. 31-34.

  11. V. Moalemi and A. Afzali-Kusha, "Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies," in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, pp. pp. 514-515.

  12. V. Moalemi and A. Afzali-Kusha, "Subthreshold Pass Transistor Logic for Ultra-Low Power Operation," in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, pp. pp. 490-491.

  13. M.A. Karami, A. Afzali-Kusha, R. Faraji-Dana, and M. Rostami, "Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution Networks," in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, pp. 488 - 489.

  14. M. Savadi-Oskoeei, A. Afzali-Kusha, S.M. Atarodi, " A High-Speed and Low-Power Voltage Controlled Oscillator in 0.18-μm CMOS Process," in Proceedings of IEEE International Symposium on Proceedings of Circuits and Systems, May 27-30, 2007, Orlando, U.S.A., pp. 933-936.

  15. M. Daneshtalab, A. Pedram, M. H. Neishaburi, M. Riazati, A. Afzali-Kusha, and S. Mohammadi, "Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections," in Proceedings of International Conference on VLSI Design, Bangalore, India, Jan. 6-10, 2007, pp. 546-560.

  16. M. Riazati, S. Mohammadi, A. Afzali-Kusha, and Z. Navabi, "Improved Assertion Lifetime via Assertion-Based Testing Methodology," in Proceedings of the 18th International Conference on Microelectronics, Saudi Arabia, Dec. 17-19, 2006, pp. 48-51.

  17. H. Parandeh-Afshar, A. Afzali-Kusha, and A. Khakifirouz, “A Very Fast and Low Power Pseudo-Incrementer for Address Bus Encoder/Decoder,” in Proceedings of the 18th International Conference on Microelectronics, Saudi Arabia, Dec. 17-19, 2006, pp. 91-94.

  18. M. Dastjerdi-Mottaghi, A. Naghilou, A. Afzali-Kusha, Z. Navabi, and M. Daneshtalab, “Hot Block Ring Counter: A Low Power Synchronous Ring Counter,” in Proceedings of the 18th International Conference on Microelectronics, Saudi Arabia, Dec. 17-19, 2006, pp. 58-62.

  19. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “A Mesochronous Technique for Communication in Network on Chips,” in Proceedings of the 18th International Conference on Microelectronics, Saudi Arabia, Dec. 17-19, 2006.

  20. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “Low-latency Multi-Level Mesh Topology for NoCs,” in Proceedings of the 18th International Conference on Microelectronics, Saudi Arabia, Dec. 17-19, 2006.

  21. E. Rahmani, Z. Pajouhi, N. Kazemian-Amiri, and A. Afzali-Kusha, “Modified Leakage-Biased Domino Circuit with Low-Power and Low-Delay Characteristics,” in Proceedings of the 18th International Conference on Microelectronics, Saudi Arabia, Dec. 17-19, 2006.

  22. A.-S. Seyedi and A. Afzali-Kusha, “Double-edge Triggered Level Converter Flip-Flop with Feedback,” in Proceedings of the 18th International Conference on Microelectronics, Dhahran, Saudi Arabia, Dec. 17-19, 2006.

  23. M. A. Karami and A. Afzali-Kusha, “Adaptive Neural Network Model for SOI-MOSFET I-V Characteristics Including Self-Heating Effects,” in Proceedings of the 18th International Conference on Microelectronics, Dhahran, Saudi Arabia, Dec. 17-19, 2006.

  24. M. A. Karami and A. Afzali-Kusha, “Exponentially Tapering Ground Wires for Elmore Delay Reduction in On-Chip Interconnects,” in Proceedings of the 18th International Conference on Microelectronics, Dhahran, Saudi Arabia, Dec. 17-19, 2006.

  25. A. Mehran, A. Khademzadeh, A. Afzali-Kusha, and B. Shirpour, “A Heuristic Energy Aware Application Mapping Algorithm for Network on Chip,” in Proceedings of IP Based SoC Design Conference & Exhibition, Grenoble, France, Dec. 6-7, 2006, pp. 289-294.

  26. F. Aezinia, A. Afzali-Kusha, and C. Lucas, “Optimizing High Speed Flip-Flop Using Genetic Algorithm,” in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, Singapore, Dec. 4-7, 2006, pp. 1789-1792.

  27. F. Aezinia, S. Najafzadeh, and A. Afzali-Kusha, “Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops,” in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, Singapore, Dec. 4-7, 2006, pp. 1413-1416.

  28. N. Honarmand and A. Afzali-Kusha, “Low Power Combinational Multiplier Using Data driven Signal Gating,” in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, Singapore, Dec. 4-7, 2006, pp. 1456-1459.

  29. M. Nazm-Bojnordi, N. Moezzi-Madani, M. Semsarzade, and A. Afzali-Kusha, “An Efficient Clocking Scheme for On-Chip Communications,” in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, Singapore, Dec. 4-7, 2006, pp. 119-122.

  30. P. Saeedi, A. Farmahini-Farahani, M. Hamzeh, and A. Afzali-Kusha, “Network-on-Chip Thermal-Balanced Mapping,” in Proceedings of International Design and Test (IDT) Workshop, Dubai, U.A.E., November 19-21, 2006.

  31. M. Daneshtalab, S. Mohammadi, A. Afzali-Kusha, and O. Fatemi, “Minimizing Hot Spots in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections,” in Proceedings of the International Symposium on System-on-Chip, Tampere, Finland, Nov. 14-16, 2006, pp. 49-52.

  32. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “Serial Bus Encoding for Low Power Application,” in Proceedings of the International Symposium on System-on-Chip, Tampere, Finland, Nov. 14-16, 2006, pp. 99-102.

  33. M. Najibi, M. Salehi, A. Afzali-Kusha, M. Pedram, S.M. Fakhraie, and H. Pedram “Dynamic Voltage and Frequency Management Based on Variable Update Intervals for Frequency Setting,” in Proceedings of the IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, Nov. 10-14, 2006.

  34. M. Daneshtalab, A. Pedram, A. Afzali-Kusha, and Siamak Mohammadi, “A New Fair Dynamic Routing Algorithm for Avoiding Hot Spots in NoCs,” in Proceedings of International Symposium on Communications and Information Technologies, Bangkok, Thailand, October 18-30, 2006.

  35. M. Daneshtalab, A. Sobhani, A. Afzali-Kusha, O. Fatemi, and Z. Navabi, “NoC Hot Spot Minimization Using AntNet Dynamic Routing Algorithm,” in Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, Steamboat Springs, Colorado, September 11-13, 2006, pp. 33-38.

  36. A. Sobhani, M. Daneshtalab, M. H. Neishaburi, M. D. Mottaghi, A. Afzali-Kusha, O. Fatemi, and Z. Navabi, “Dynamic Routing Algorithm for Avoiding Hot Spots in On-chip Networks,” in Proceedings of the IEEE International Conference on Design & Test Integrated Systems in Nanoscale Technology, Tunis, Tunisia, Sept. 5-7, 2006, pp. 179-183.

  37. M. Daneshtalab, A. Sobhani, M. D. Mottaghi, A. Afzali-Kusha, Z. Navabi, and O. Fatemi, “Ant Colony Based Routing Architecture for Minimizing Hot Spots in NOCs,” in Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006, Ouro Preto, Brazil, Aug. 28 – Sept. 01, 2006, pp. 56-61.

  38. M. D. Mottaghi, A. Afzali-Kusha, and Z. Navabi, “ByZFAD: A Low Switching Activity Architecture for Shift-and-Add Multipliers,” in Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006, Ouro Preto, Brazil, Aug. 28 – Sept. 01, 2006, pp. 179-183.

  39. A.R. Aminlou, M.M. Khafaji, V. Moalemi, and A. Afzali-Kusha, “A Low-Power Low-Voltage Full Adder Cell using Latched XOR-XNOR,” in Proceedings of 3rd International Conference on Circuits and Systems for Communications, Bucharest, Romania, July 6-7, 2006, pp 15-18.

  40. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, A. Afzali-Kusha, and C. Lucas, “Design of Domino Logic Circuits by an Optimization Method,” in Proceedings of Mixed Design of Integrated Circuits and Systems, Gdynia, Poland, 22-24 June 2006.

  41. A.R. Saberkari, A. Afzali-Kusha, and S. Baradaran-Shokouhi, “Design of a Low-Power Low-Voltage 1-bit Adder Cell Using GDI Technique,” in Proceedings of 14th Iranian Conference on Electrical Engineering, Tehran, Iran, May 16-18, 2006.

  42. S.G. Razavipour, S.A. Motamedi, and A. Afzali-Kusha, “Low-Power High-Speed SRAM Cell for Lowe-Power Applications,” in Proceedings of 14th Iranian Conference on Electrical Engineering, Tehran, Iran, May 16-18, 2006.

  43. M. Salehi, M. Najibi, H. Pedram, A. Afzai-Kusha, and S.M. Fakhraei, “Implementation of DVFM Control System for Processor Power Reduction,” in Proceedings of 14th Iranian Conference on Electrical Engineering, Tehran, Iran, May 16-18, 2006.

  44. A. Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, and A. Afzai-Kusha, “Low Power and High Performance Clock Delayed Domino Logic using Saturated Keeper in sub 100nm Technologies,” in Proceedings of 14th Iranian Conference on Electrical Engineering, Tehran, Iran, May 16-18, 2006.

  45. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, and A. Afzali-Kusha, “Genetic Algorithm Method for Design of Domino Logic Circuits,” in Proceedings of 14th Iranian Conference on Electrical Engineering, Tehran, Iran, May 16-18, 2006.

  46. H. Parandeh-Afshar, A. Afzali-Kusha, and A. Khakifirooz “A Very High Performance Address BUS Encoder,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24, 2006, pp. 1731-17324.

  47. N. Honarmand, M.R.Javaheri, N.Sedaghati-Mokhtari and A. Afzali-Kusha, “Power Efficient Sequential Multiplication Using Pre-computation,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24, 2006, pp. 2709-2712.

  48. B. Kheradmand-Boroujeni, F. Aezinia, and A. Afzali-Kusha, “High Performance Circuit Techniques for Dynamic OR Gates,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24, 2006, pp. 3662-3666.

  49. S. Mehrmanesh, B. Eghbalkhah, S. Saeedi, A. Afzali-Kusha, and M. Atarodi “A Compact Low Power Mixed-Signal Equalizer for Gigabit Ethernet Applications,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24, 2006, pp. 5167-5170.

  50. G. Razavipour, A. Motamedi, and A. Afzali-Kusha, “WL-VC SRAM: A Low Leakage Memory Circuit for Deep Sub-Micron Design,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24, 2006, pp. 2237-2240.

  51. M. Riazati, A. Sobhani, M. Mottaghi-Dastjerdi, A. Afzali-Kusha, and A. Khakifirooz, “Low-Power Multiplier with Static Decision for Input Manipulation,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24, 2006, pp. 2721-2724.

  52. M Saneei, A Afzali-Kusha, and Z Navabi, “Low-power and Low-latency Cluster Topology for Local Traffic NoCs,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24, 2006, pp. 1727-1730.

  53. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, and A. Afzali-Kusha, “Low Power Low Leakage Clock Gated Static Pulsed Flip-Flop,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24, 2006, pp. 3658-3661.

  54. A. Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, and A. Afzai-Kusha, “Low Power and High Performance Clock Delayed Domino Logic using Saturated Keeper,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24, 2006, pp. 3173-3176.

  55. Masood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha, and Zainalabedin Navabi, “A New Protocol Stack Model for Network on Chip,” in the Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, March 2006, Germany, pp. 440 – 441.

  56. A. S. Seyedi, S. H. Rasouli. A. Amirabadi, and A. Afzali-Kusha, “Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology,” in the Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, March 2006, Germany, pp. 373 – 377.

  57. S. H. Rasouli, A. Amirabadi,  A. S. Seyedi, and A. Afzali-Kusha, “Double Edge Triggered Feedback flip-flop in Sub 100nm Technology,” in the Proceedings of Asia and South Pacific Conference on Design Automation, 2006, Japan, pp. 297 – 302.

  58. P. Hashemi, J. Derakhshandeh, S. Mohajerzadeh, M.D. Robertson, J.C. Bennett, A. Shayan-Arani, and A. Afzali-Kusha, “Characterization of Low Temperature Stress-Induced Crystallization of a-Si on Flexible Glass Substrate by Transmission Electron Microscopy and Raman Spectroscopy,” in Proceedings of the 17th International Conference on Microelectronics, Islamabad, Pakistan, December 13-15, 2005, pp. 326-329.

  59. M. Nazm-Bojnordi, M. Semsarzadeh, A. Banaiyan, and Ali Afzali-Kusha, “A Simple, Low-Cost and Low-Power Switch Architecture for NoCs,” in Proceedings of the 17th International Conference on Microelectronics, Islamabad, Pakistan, December 13-15, 2005, pp. 194-197.

  60. M. Dehyadgari, M. Nickray,  A. Afzali-Kusha, and Z. Navabi, “Evaluation of Pseudo Adaptive XY Routing Using an Object Oriented Model for NOC,” in Proceedings of the 17th International Conference on Microelectronics, Islamabad, Pakistan, December 13-15, 2005, pp. 204-208.

  61. M. Dehyadgari, M. Nickray,  A. Sobhani, and A. Afzali-Kusha, “Multiplier for Correlative Input Patterns,” in Proceedings of the 17th International Conference on Microelectronics, Islamabad, Pakistan, December 13-15, 2005, pp. 72-74.

  62. V. Majidzadeh, S. M. Alavi, and A. Afzali-Kusha, “Design of Merged Differential Cascode Voltage Switch with Pass-Gate (MDCVSPG) Logic for High-Performance Digital Systems,” in Proceedings of the 17th International Conference on Microelectronics, Islamabad, Pakistan, December 13-15, 2005, pp. 63-66.

  63. B. Kheradmand-Boroujeni, A. Seyyedi, and A. Afzali-Kusha, “High Speed Low Gate Leakage Large Capacitive-Load Driver Circuits for Low-Voltage CMOS,” in Proceedings of the 17th International Conference on Microelectronics, Islamabad, Pakistan, December 13-15, 2005, pp. 30-35.

  64. B. Kheradmand-Boroujeni, K. Shojaee, and A. Afzali-Kusha, “Design and Simulated Annealing Optimization of a Static Comparator for Low-Power High-Speed CMOS VLSI,” in Proceedings of the 17th International Conference on Microelectronics, Islamabad, Pakistan, December 13-15, 2005, pp. 355-359.

  65. B. Kheradmand-Boroujeni and A. Afzali-Kusha, “A New Static High Fan-In OR-NOR Gate Structure Suitable for Low Power CMOS VLSI,” in Proceedings of the 17th International Conference on Microelectronics, Islamabad, Pakistan, December 13-15, 2005, pp. 102-105.

  66. A. Amirabadi, Y. Mortazavi, and A. Afzali-Kusha, “An Efficient Forward Biasing Body Bias Generator for Clock Delayed Domino Logic,” in Proceedings of the 17th International Conference on Microelectronics, Islamabad, Pakistan, December 13-15, 2005, pp. 13-18.

  67. M. Dehyadgari, M. Nickray, and A. Afzali-Kusha, “Power and Delay Optimization for Network on Chip,” in Proceedings of European Conference on Circuit Theory and Design (ECCTD’05), Ireland, 2005, pp. III-277–III-281.

  68. M. Dehyadgari, M. Nickray, and A. Afzali-Kusha, “Low Power Communication for Network on Chip,” in Proceedings of International Symposium on Telecommunications (IST’05), Shiraz, Iran, 2005, pp. 521-525.

  69. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “Sign Bit Reduction Encoding For Low Power Applications,” in Proceedings of 15th Design Automation Conference, Anaheim, U.S.A., June 2005, pp. 213-217.

  70. A. Abbasian, M. Taherzadeh-Sani, B. Amelifard, and A. Afzali-Kusha, “Modeling of MOS Transistors Based on Genetic Algorithm and Simulated Annealing,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005, pp. 6218-6221.

  71. B. Afzal, A. Afzali-Kusha, and M. El Nokali, “Efficient Power Model for Crossbar Interconnects,” in 2005 Proceedings of IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005, pp. 5858-5861.

  72. B. Amelifard, A. Afzali-Kusha, and A. Khademzadeh, “Enhancing the Efficiency of Cluster Voltage Scaling Technique for Low-power Applications,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005, pp. 1666-1669.

  73. A. Amirabadi, Y. Mortazavi, N. Moezzi-Madani, A. Afzali-Kusha, and M. Nourani, “Domino Logic with an Efficient Variable Threshold Voltage Keeper,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005, pp. 1674-1677.

  74. M. Gholipour, K. Shojaee, A. Afzali-Kusha, A. Khademzadeh, and M. Nourani, “An Efficient Model for Performance Analysis of Asynchronous Pipeline Design,” in Proceedings of 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005, pp. 5236-5239.

  75. S. Hatami, M. Alisafaee, E. Atoofian, Z. Navabi, and A. Afzali-Kusha, “A Low-Power Scan-Path Architecture,” in 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005, pp. 5278-5281.

  76. A. Amirabadi, Y. Mortazavi, and A. Afzali-Kusha, “Clock Delayed Domino Logic with an Efficient Variable Voltage Keeper Threshold,” in Proceedings of 13th Iranian Conference on Electrical Engineering, Zanjan, Iran, May 10-12, pp. 416-420.

  77. R. Safa-Isini, Gh. Razavipour, and A. Afzali-Kusha, “A Self-Controllable Voltage Level Circuit with Body Biasing for Low Power Applications,” in Proceedings of 13th Iranian Conference on Electrical Engineering, Zanjan, Iran, May 10-12, 2005, pp. 167-171.

  78. S. Toofan, A. Afzali-Kusha, A. Ale-Ahmad, and A. Rahmati “New Current Mode Amplifier for Low-Power Low-Voltage SRAMs in Proceedings of 13th Iranian Conference on Electrical Engineering, Zanjan, Iran, May 10-12, 2005, pp. 109-112.

  79. A.A. Shirazai-Beheshti, E. Rouhani, K. Abdi, and A. Afzali-Kusha, “Improved Alpha-Power Model For MOSFETs,” in Proceedings of 13th Iranian Conference on Electrical Engineering, Zanjan, Iran, May 10-12, 2005, pp. 79-84.

  80. M. Nickray, M. Dehyadgari, A. Sobhani, and A. Afzali-Kusha, “LPPM: Low Power Partitioned Multiplier,” in Proceedings of 13th Iranian Conference on Electrical Engineering, Zanjan, Iran, May 10-12, 2005.

  81. V. Majidzadeh, S. M. Alavi, and A. Afzali-Kusha, “Design of Merged Differential Cascade Voltage Switch with Pass-Gate (MDCVSPG) Logic for High-Performance Digital Systems,” in Proceedings of 13th Iranian Conference on Electrical Engineering, Zanjan, Iran, May 10-12, 2005.

  82. B. Afzal and A. Afzali-Kusha, “Speed Improvement of 16×16 Multipliers using Sizing Optimization by Genetic Algorithm,” in Proceedings of 13th Iranian Conference on Electrical Engineering, Zanjan, Iran, May 10-12, 2005, pp. 130-134.

  83. B. Afzal and A. Afzali-Kusha, “Optimized Design of Wallace Tree in Direct Form Block by Genetic Algorithm,” in Proceedings of 13th Iranian Conference on Electrical Engineering, Zanjan, Iran, May 10-12, 2005, pp. 321-325.

  84. S. Sharifi, J. Jaffari, A. Hosseinabadi, A. Afzali-Kusha, and Z. Navabi, “Simultaneous Reduction of Dynamic and Static Power in Scan Structures,” in Proceedings of the 15th Design, Automation and Test in Europe, 7-11 March, Munich, Germany, 2005, pp. 846 - 851.

  85. M. Alisafaee, S. Hatami, E. Atoofian, Z. Navabi and A. Afzali-Kusha, “Architecture of a Data Compression-based Low-power Scan-path,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, 2004, pp. 768-771.

  86. M. Saneei, A. Afzali-Kusha, and Z. Navabi, “A Low Power Technique Based on Sign Bit Reduction,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, 2004, pp. 497-500.

  87. A. Amirabadi, Y. Mortazavi, and A. Afzali-Kusha, “Optimizing Low-Power High-Speed Full Adders With Simulated Annealing,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, pp. 429-432, 2004.

  88. J. Jaffari and A. Afzali-Kusha, “New Dual-Threshold Voltage Assignment Technique for Low-Power Digital Circuits,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, pp. 413-416, 2004.

  89. M. Gholipour, K. Shojaee, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani, “Performance and Power Analysis of Asynchronous Pipeline Design Methods,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, pp. 409-412, 2004.

  90. P. Hashemi, A. Behnam, E. Fathi, and A. Afzali-Kusha, “Two-Dimensional Analytical Modeling and Simulation of the Potential and Threshold Voltage of a New Fully Depleted Dual Metal Gate SOI MESFET,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, pp. 372-375, 2004.

  91. M. Taherzadeh-Sani, A. Abbasian, B. Amelifard, and A. Afzali-Kusha, “MOS Compact I-V Modeling with Variable Accuracy Based on Genetic Algorithm and Simulated Annealing,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, pp. 364-367, 2004.

  92. B. Afzal and A. Afzali-Kusha “Power Estimation of Crossbar Interconnects Using Fully Analytical Approach,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, pp. 219-222, 2004.

  93. J. Jaffari and A. Afzali-Kusha, “A Novel Technique for Reducing Leakage Current of VLSI Combinational Circuits,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, pp. 207-210, 2004.

  94. N. Moezzi-Madani, B. Tavassoli, A. Behnam, and A. Afzali-Kusha, “Study of Super Cut-Off CMOS Technique in Presence of the Gate Leakage Current,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, pp. 24-27, 2004.

  95. F. Farbiz, A. Behnam, M. Emadi, B. Esfandiarpoor, and A. Afzali-Kusha, “Voltage and Sizing Optimization for Low Power Buffered Digital Designs,” in Proceedings of the 16th International Conference on Microelectronics, Tunis, Tunisia, December 6-8, pp. 20-23, 2004.

  96. M. H. Tehranipour, M. Nourani, K. Arabi and A. Afzali-Kusha, “Mixed RL-Huffman Encoding for Power Reduction and Data Compression in Scan Test,” in Proceedings of 2004 IEEE International Symposium on Circuits and Systems, Vancouver, Canada, May 23-26, pp. II681-II684, 2004.

  97. A. Abbasian, S. Hatami, A. Afzali-Kusha, M. Nourani, and C. Lucas “Event-Driven Dynamic Power management Based on Wavelet Forecasting Theory,” in Proceedings of 2004 IEEE International Symposium on Circuits and Systems, Vancouver, Canada, May 23-26, pp. V325-V328, 2004.

  98. A. Abbasian, S. Hatami, A. Afzali-Kusha, C. Lucas, and M.R. Zamani, “Wavelet Based Dynamic Power Management for Nonstationary Service Requests,” in the Proceedings of 12th Iranian Conference on Electrical Engineering, Mashhad, Iran, May 11-13, 2004, vol. 1, pp. 226-231.

  99. B. Afzal, E. Fathi, A.L. Baghestani, A. Afzali-Kusha, and M. Nourani, “Power Estimation of Crossbar Interconnect using Fully Analytical Approach,” in the Proceedings of 12th Iranian Conference on Electrical Engineering, Mashhad, Iran, May 11-13, 2004, vol. 1, pp. 192-197.

  100. A. Zahabi, Y. Koolivand, A. Afzali-Kusha, and M. Nourani, “Area and Power Optimization Method for High-Speed Dual VT Domino Logic with Noise Constraint,” in the Proceedings of 12th Iranian Conference on Electrical Engineering, Mashhad, Iran, May 11-13, 2004, vol. 1, pp. 103-108.

  101. J. Jafari, A. Amirabadi, and A. Afzali-Kusha, “A Novel Technique for Reducing Subthreshold Current of VLSI Combinational Circuits,” in the Proceedings of 12th Iranian Conference on Electrical Engineering, Mashhad, Iran, May 11-13, 2004, vol. 1, pp. 163-167.

  102. A. Amirabadi, R.A. Tousi, J. Jafari, and A. Afzali-Kusha, “Leakage Current Reduction by New Technique in Standby Mode,” in the Proceedings of 12th Iranian Conference on Electrical Engineering, Mashhad, Iran, May 11-13, 2004, vol. 1, pp. 46-51.

  103. S. H. Rasouli, A. Afzali-Kusha, A. Khademzadeh, and M. Nourani, “Double Edge Triggered Modified Hybrid Latch Flip-flop (DMHLFF),” in the Proceedings of 12th Iranian Conference on Electrical Engineering, Mashhad, Iran, May11-13, 2004, vol. 1, pp. 139-144.

  104. S.H. Rasouli, A. Afzali-Kusha, A. Khademzadeh, M.H. Tehranipour, M. Nourani “A New Test Pattern Generator by Altering the Structure of 2-D LFSR for Built-in Self Test Applications,” in the Proceedings of 12th Iranian Conference on Electrical Engineering, Mashhad, Iran, May 11-13, 2004, vol. 1, pp. 259-264.

  105. D. Shahrjerdi, B. Hekmatshoar, A. Afzali-Kusha, and A Khakifirooz, “Optimization of the VT-Control Method for Low-Power Ultra-Thin Double-Gate SOI Logic Circuits,” in Proceedings of The 2004 Great Lakes Symposium on VLSI (GLSVLSI’04), pp. 236-239, April 26-28, 2004, Boston, Massachusetts, U.S.A.

  106. A. Amirabadi, J. Jafari, A. Afzali-Kusha, M. Nourani, and A. Khakifirooz, “Leakage Current Reduction by New Technique in Standby Mode,” in Proceedings of The 2004 Great Lakes Symposium on VLSI (GLSVLSI’04), pp. 158-161, April 26-28, 2004, Boston, Massachusetts, U.S.A.

  107. R. Dehghani, S.M. Atarodi, B. Bornoosh, and A. Afzali Kusha, “A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis,” in Proceedings of the 17th International Conference on VLSI Design, January 05-09, 2004, pp. 615-618, Mumbai, India.

  108. A. Abbasian, A.M. Nasri-Nasr Abadi, and A. Afzali-Kusha, “Modular Energy Recycling Differential Logic (MERDL) for Low Power Applications,” in Proceedings of 10th IEEE International Conference on Electronics, Circuits and Systems, Dec. 14-17, 2003, pp. 312-315, Sharjah, United Arab Emirates, 2003.

  109. A. Abbasian and A. Afzali-Kusha, “Pipeline Event-driven No-race Charge Recycling Logic (PENCL) for Low Power Applications,” in Proceedings of 10th IEEE International Conference on Electronics, Circuits and Systems, Dec. 14-17, 2003, pp. 220-223, Sharjah, United Arab Emirates, 2003.

  110. S. H. Rasouli, A. Afzali-Kusha, A. Khademzadeh, and M. Nourani, “Low-Race Split-level Charge-Recycling Pass-Transistor Logic (LSCPL) for Low Power High Speed Applications,” in Proceedings of the 15th International Conference on Microelectronics, Dec. 9-11, 2003, Cairo, Egypt, pp. 243-246, 2003.

  111. E. Atoofian, S. Hatami, Z. Navabi, M. Alisafaee, and A. Afzali-Kusha, “A New Low-Power Scan-Path Architecture,” IEEE 4th Workshop on RTL and High Level Testing, pp. 91-95, November 20-21, 2003, XI’AN, China.

  112. M. Naderi, B. Javadi, H. Pedram, A. Afzali-Kusha, and M. K. Akbari, “An Asynchronous Viterbi-Decoder for Low-Power Applications”, in Proceedings of International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2003), Torino, Italy, September 10-12, pp. 471-480, Italy, Sep. 2003.

  113. M. H. Tehranipour, M. Nourani, S. M. Fakhraie, and A. Afzali-Kusha, “Systematic Test Program Generation for SoC Testing Using Embedded Processor,” in Proceedings of 2003 IEEE International Symposium on Circuits and Systems, pp. V541-V544, Bangkok, Thailand, May 25-28, 2003.

  114. M. Yavari, O. Shoaei, and A. Afzali-Kusha, “A Very Low-Voltage, Low-Power and High Resolution Sigma-Delta Modulator for Digital Audio in 0.25-mm CMOS,” in Proceedings of 2003 IEEE International Symposium on Circuits and Systems, pp. I1045-I1048, Bangkok, Thailand, May 25-28, 2003.

  115. A. Abbasian, S.H. Rasouli, A. Afzali-Kusha, and M. Nourani, “No-race Pass Transistor Logic (NCRPL) for Low Power Applications,” in Proceedings of 2003 IEEE International Symposium on Circuits and Systems, pp. V289-V292, Bangkok, Thailand, May 25-28, 2003.

  116. B. Amelifard, M. Taherzadeh-Sani, H. Iman-Eini, and A. Afzali-Kusha, “Delay and Power Estimation of CMOS Inverters,” in Proceedings of 11th Iranian Conference on Electrical Engineering, Shiraz, May 6-8, 2003, vol. 1, pp. 458-464.

  117. H. Iman-Eini, M. Taherzadeh-Sani, B. Amelifard, and A. Afzali-Kusha, “Reducing CMOS Gates to Equivalent Inverters Based on Modified n-th Power Law MOSFET Model,” in the Proceedings of 11th Iranian Conference on Electrical Engineering, Shiraz, Iran, May 6-8, 2003, vol. 1, pp. 452-457.

  118. A. Abbasian, S.H. Rasouli, A. Afzali-Kusha, and A. Khademzadeh, “MRFCPL: A new charge recycling logic with no sensitivity to signal skew for low-power applications,” in the Proceedings of 11th Iranian Conference on Electrical Engineering, Shiraz, Iran, May 6-8, 2003, vol. 1, pp. 26-33. (in Persian).

  119. M. Nourani, A. Afzali-Kusha, J. Carletta, and C. Papachristou “Effect of Don't Cares on SoC's Testability and Power,” in Proceedings of 8th Annual International Computer Society of Iran Computer Conference, Mashad, Iran, Feb. 25-27, pp. 60-67, 2003.

  120. M. Taherzadeh-Sani, B. Amelifard, H. Iman-Eini, M. Farazian, A. Afzali-Kusha, and M. Nourani “A simple yet accurate analytical method for reducing CMOS gates to equivalent inverters,” in Proceedings of the 2003 Southwest Symposium on Mixed-Signal Design, Las Vegas, U.S.A., 23-25 February, pp. 116-120, 2003.

  121. M. Taherzadeh-Sani, B. Amelifard, H. Iman-Eini, F. Farbiz, A. Afzali-Kusha, and M. Nourani “Power and Delay Estimation of CMOS Inverters Using Fully Analytical Approach,” in Proceedings of the 2003 Southwest Symposium on Mixed-Signal Design, Las Vegas, U.S.A., 23-25 February, pp. 112-115, 2003.

  122. A. Abbasian, S.H. Rasouli, J. Derakhshandeh, A. Afzali-Kusha, and M. Nourani “Race-free CMOS PASS-gate Charge Recycling Logic (FCPCL) For Low Power Applications,” in Proceedings of the 2003 Southwest Symposium on Mixed-Signal Design, Las Vegas, U.S.A., 23-25 February, 2003, pp. 87-89, 2003.

  123. S. Hatami, M.Y. Azizi, H.R. Bahrami, D. Motavalizadeh and A. Afzali-Kusha, “SOI MOSFET I-V Characteristics Modeling by Neural Networks,” in Proceedings of the 14th International Conference on Microelectronics, Beirut, Lebanon, December 11-13, pp. 114-117, 2002.

  124. M. Nourani, S. Nazarian, and A. Afzali-Kusha, “A Parallel Algorithm for Power Estimation at Gate Level,” in Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August 4-7, 2002.

  125. M. Gholipour, A. Afzali-Kusha, M. Nourani, and A. Khademzadeh, “An Efficient Asynchronous Pipeline FIFO for Low-Power Applications,” in Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August 4-7, 2002.

  126. M. Maddah, A. Afzali-Kusha, H. Soltanian-Zadeh, “Efficient Medial Curve Extraction of Microvascular Structures in Confocal Microscopy Images,” in Proceedings of International Conference on Diagnostic Imaging and Analysis, Shanghai, China, 18-20 August, 2002.

  127. M. Maddah, A. Afzali-Kushaa, H. Soltanian-Zadeh, “Fast centerline extraction for quantification of vessels in Confocal Microscopy images,” in Proceedings of 2002 IEEE International Symposium on Biomedical Imaging, Washington, D.C., 7-10 July, 2002.

  128. H. Mahmoodi-Meimand and A. Afzali-Kusha, “Efficient Power Clock Generation For Adiabatic Logic,” in Proceedings of 2001 IEEE International Symposium on Circuits and Systems, Sydney, Australia, May 6-9, 2001.

  129. H. Mahmoodi-Meimand and A. Afzali-Kusha, “Low-Power, Low-Noise Adder Design with Pass-transistor Adiabatic Logic,” in Proceedings of International Conference of Microelectronics, Tehran, Iran, Oct. 31- Nov. 2, 2000.