Mehdi Kamal

Assistant Professor

 

 

mehdikamal [AT] ut.ac.ir

Tel: (+98 21) 8208-4212

 

Research Interests & Experiences

  1. Digital embedded system design
  2. Approximate computing & Neuromorphic computing
  3. Design for manufacturability
  4. System-level HW/SW Co-design
  5. Low power design
  6. Testability and design for test

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Education

  • 2008-2013: PhD student, Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran.

  • Jan.-July 2012: Visiting Scholar, SPORT lab, Department of Electrical Engineering, University of Southern California

  • 2005-2007: MS student, Computer Engineering, Sharif University of Technology, Tehran, Iran.
  • 2001-2005: BS student, Computer Engineering, Iran University of Science and Technology, Tehran, Iran.

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Professional Services

  • Member: Program Committe, ISLPED, 2016-2017
  • Member: Program Committe, GLSVLSI, 2016-2017
  • Reviewer: IEEE TVLSI,IEEE TCAS-II, Journal of Parallel and Distributed Computing, Electrical Engineering.

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Publications

Book Chapter

  1. M. Hemmat, M. Kamal, A. Afzali-Kusha, M. Pedram, “Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors”, in VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, Th. Hollstein, et al., 2017.

Journal

  1. S. S. Nabavi Larimi, M. Kamal, A. Afzali-Kusha, “BIMS: Built-in Intermediate Memory Structure to Improve Multi-Level Phase Change Memories,” Accepted in Tabriz Journal of Electrical Engineering, 2017.
  2. S. Sadeghi-Kohan, M. Kamal, and Z. Navabi, “Self-Adjusting Monitor for Measuring Aging Rate and Advancement”, Accepted in IEEE Transactions on Emerging Topics in Computing, 2017.
  3. F. Nakhaee, M. Kamal, A. Afzali-Kusha, M. Pedram, and S. M. Fakhraie, H. Dorosti, “Lifetime Improvement by Exploiting Aggressive Voltage Scaling during Runtime of Error-resilient Applications, “ Accepted in Integrated, the VLSI, 2017.
  4. M. Ansari, A. Fayyazi, A. Banagozar, M.A. Maleki, M. Kamal, A. Afzali-Kusha, and M. Pedram, “PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits,“ Accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.
  5. A. Iranfar, M. Kamal, A. Afzali-Kusha, D. Atienza, and M. Pedram, “TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip,” Accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.
  6. S. Vahdat, M. Kamal, A. Afzali-Kusha, and M. Pedram, “LETAM: A Low Energy Truncation-based Approximate Multiplier,“ Elsevier Journal of Computers and Electrical Engineering, vol. 63, pp. 1-17, 2017.
  7. S. Abolmaali, M. Kamal, A. Afzali-Kusha, M. Pedram, “Efficient Critical Path Identification based on Viability Analysis Method Considering Process Variations,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.(25), no.(9), pp. 2668-2672,2017.
  8. M. Bahadori, M. Kamal, A. Afzali-Kusha, and M. Pedram, “An Energy and Area Efficient yet High-Speed Square-Root Carry Select Adder Structur,”Elsevier Journal of Computers and Electrical Engineering, vol. 58, pp. 101-112, 2017.
  9. O. Akbari, M. Kamal, A. Afzali-Kusha, and Massoud Pedram, “Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers,” Accepted in IEEE Transactions on Very Large Scale Integration Systems(TVLSI), vol. 25, no. 4, pp. 1352-1361, 2016.
  10. M. Bahadori , M. Kamal , A. Afzali-Kusha , Y . Afsharnezhad, E . Z . Salehi, “CL-CPA: A Hybrid Carry-Lookahead/Carry-Propagate Adder for Low-Power or High-Performance Operation Mode,” Elsevier Integration, the VLSI journal, vol. 54, pp. 62-58, 2017.
  11. O. Akbari, M. Kamal, A. Afzali-Kusha, and Massoud Pedram, “RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder,” Accepted in IEEE Transactions on Circuits and Systems II (TCAS-II), 2016.
  12. M. Hemmat, M. Kamal, A. Afzali-Kusha, and M. Pedram, “Hybrid TFET-MOSFET Circuit: A Solution to Design Soft-Error Resilient Ultra-Low Power Digital Circuit,” Elsevier Integration, the VLSI journal, vol. 57, pp. 11-19, 2017.
  13. R. Zendegani, M. Kamal, M. Bahadori, A. Afzali-Kusha, and Massoud Pedram, “RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing,” IEEE Transactions on Very Large Scale Integration Systems(TVLSI), vol. 25, no. 2, pp. 393-401, 2016.
  14. M. Hemmat, M. Kamal, A. Afzali-Kusha, and M. Pedram, “Study On the Impact of Device Parameter Variations on Performance of III-V Homojunction and Heterojunction Tunnel FETs,” Solid-State Electronics, vol. 124, pp. 46-53, 2016.
  15. Ahmadi-Balef, M. Kamal, A. Afzali-Kusha, and M. Pedram, "All-Region Statistical Model for Delay Variation based on Lxog-Skew-Normal Distribution,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 35, no. 9, pp. 1503-1508, 2016.
  16. M. Bahadori, M. Kamal, A. Afzali-Kusha, and M. Pedram, “A Comparative Study on Performance and Reliability of 32-bit Binary Adders,”Elsevier Integration, the VLSI journal, vol. 53, pp. 54-67, 2016.
  17. M. Kamal, Q. Xie, M. Pedram, A. Afzali-Kusha, and S. Safari. “An Efficient Temperature Dependent Hot Carrier Injection Reliability Simulation Flow,” Elsevier Journal of Microelectronics Reliability, vol. 57, pp.10-19, 2016.
  18. M. Kamal, A. Afzali-Kusha, S. Safari, and M. Pedram, “Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 21, no.2, Article No. 8, 2016.
  19. M. Bahadori, M. Kamal, A. Afzali-Kusha, and M. Pedram. “High-Speed and Energy-Efficient Carry Skip Adder Operating under a Wide Range of Supply Voltage Levels,” IEEE Trans. on VLSI Systems, vol. 24, no.2, pp.421-433, 2016.
  20. M. Kamal, A. Afzali-Kusha, S. Safari, and M. Pedram, “OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Data Flow Graphs,” ACM Transactions on Embedded Computing, vol. 14, no. 4, Article No. 72, 2015.
  21. B. Eghbalkhah, M. Kamal, A. Afzali-Kusha, M. B. Ghaznavi-Ghoushchi, and M. Pedram, “Workload and Temperature Dependent Evaluation of BTI-Induced Lifetime Degradation in Digital Circuits,” Elsevier Journal of Microelectronics Reliability, vol. 55, pp. 1152-1162, 2015.
  22. M. Kamal, A. Afzali-Kusha, S. Safari, and M. Pedram, “Design of NBTI-resilient extensible processors,” Elsevier Integration, the VLSI journal, vol. 49, pp. 22-34, 2015.
  23. V. Akhlaghi, M. Kamal, A. Afzali-Kusha, and M. Pedram, “An efficient network on-chip architecture based on isolating local and non-local communications,” Elsevier Journal of Computers and Electrical Engineering, In Press, 2014.
  24. B. Eghbalkhah, M. Kamal, A. Afzali-Kusha, M.B. Ghaznavi-Ghoushchi, and M. Pedram,”CSAM: A Clock Skew-aware Aging Mitigation Technique", to appear in Elsevier Microelectronics Reliability, 2014.
  25. A. Yazdanbakhsh, M. Kamal, S.M. Fakhraie, A. Afzali-Kusha, S. Safari, and M. Pedram,” Implementation-aware selection of the custom instruction set for extensible processors", to appear in Elsevier Microprocessors and Microsystems, 2014.
  26. M. Kamal, A. Yazdanbakhsh, H. Noori, A. Afzali-Kusha, and M. Pedram,"A New Merit Function for Custom Instruction Selection under an Area Budget Constraint", Journal of Design of Automation for Embedded Systems (DAEM), Vol. 17, No. 1, pp. 1-25, 2013.
  27. M. Kamal, A. Afzali-Kusha, S. Safari, and M. Pedram, "Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors", ACM Journal on Emerging Technologies in Computing Systems, Vol. 10, No. 3, Article No. 19, 2013.
  28. M. Kamal, A. Afzali-Kusha, S. Safari, and M. Pedram "Considering the effect of process variations during the ISA extension design flow," Elsevier Microprocessors and Microsystems, Vol. 37, No. 6-7, pp. 713-724, 2013.
  29. M. Kamal, S. Koohi, S. Hessabi, "GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses," Elsevier Journal of Microprocessors & Microsystems, Vol. 35, pp. 68-80, Feb. 2011.

Conference

  1. S. Vahdat, M. Kamal, A. Afzali-Kusha, M. Pedram, Z. Navabi, TruncApp: A Truncation-based Approximate Divider for Energy Efficient DSP Applications,” Accepted in Design Automation and Test in Europe (DATE) conference, 2017.
  2. A. BanaGozar, M. A. Maleki, M. Kamal, A. Afzali-Kusha, and M. Pedram, “Sustainable Neuromorphic Computing in the Presence of Process Variation,” Accepted in Design Automation and Test in Europe (DATE) conference, 2017.
  3. M. Hemmat, M. Kamal, A. Afzali-Kusha, and M. Pedram, “Hybrid TFET-MOSFET Circuits: An Approach to Design Reliable Ultra-Low Power Circuits in the presence of Process Variation,“ in Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016.
  4. Nabavi Larimi, M. Kamal, A. Afzali-Kusha, and H. Mahmoodi, “Power and Energy Reduction of Racetrack-based Caches by Exploiting Shared Shift Operations,“ in Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016.
  5. R. Zendegani, M. Kamal, A. Afzali-Kusha, and Massoud Pedram, “SEERAD: A High Speed yet Energy-Efficient Rounding-based Approximate Divider”, in Proceedings of Design Automation and Test in Europe (DATE) conference, 2016, pp. 1481-1484.
  6. A. Iranfar, S. Shahsavani, M. Kamal, A. Afzali-Kusha, “A Heuristic Machine Learning-based Algorithm for Power and Thermal Management of Heterogeneous MPSoCs,” In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), 2015, pp. 291-296.
  7. S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online self adjusting progressive age monitoring of timing variations,” In Proceedings International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015.
  8. M. Kamal, A. Iranfar, A. Afzali-Kusha, M. Pedram, “A Thermal Stress-Aware Algorithm for Power and Temperature Management of MPSoCs,” Proceedings of Design Automation and Test in Europe (DATE) conference, 2015, pp. 954-059.
  9. P. Foroutan, M. Kamal, Z. Navabi, “A Heuristic Path Selection Method for Small Delay Defects Test,”Proceedings of Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTs), 2014, pp. 252-257.
  10. M. Kamal, A. Ghasem-Azar, A. Afzali-Kusha, M. Pedram, “Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions,” Proceedings of Design Automation and Test in Europe (DATE) Conference, 2014.
  11. M.Kamal, A. Afzali-Kusha, S. Safari, M. Pedram, and B. Eghbalkhah, "Capturing and Mitigating the NBTI Effect Duringthe Design Flow for Extensible Processors," Proc. of Design and Technology of Integrated Systems in Nanoscale Era(DTIS), 2013, pp. 180-183.
  12. V. Akhlaghi, M. Kamal, A. Afzali-Kusha, and M. Pedram. "An Efficient Network on-Chip Architecture Based on Isolating Local and non-Local Communications," To appear in Proc. of Design Automation and Test in Europe, Mar. 2013.
  13. M. Kamal, Q. Xie, M. Pedram, A. Afzali-Kusha, and S. Safari. "An Efficient Reliability Simulation Flow for Evaluating the Hot Carrier Injection Effect in CMOS VLSI Circuits," Proc. of the Int'l Conf. on Computer Design, Oct. 2012, pp. 352-357 (Best Paper Award).
  14. M. Kamal, A. Afzali-Kusha, A. Safari, and M. Pedram. " An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors," in Proceedings of the Design, Automation and Test in Europe (Date), 2012, pp. 467-472.
  15. S. Abbaspour,  M. Kamal,  H. Noori, and S. Safari, ”Securing Embedded Processors against Power Analysis based Side Channel Attacks using Reconfigurable Architecture”, in Proceedings of the 9th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Melbourne, 2011, pp. 255-260. 
  16. M. Kamal, A. Afzali-Kusha, and M. Pedram. "Timing variation-aware custom instruction extension technique," in Proceedings of the Design, Automation and Test in Europe (Date), 2011, pp. 1517-1520.
  17. A. Yazdanbakhsh, M. Kamal, Mostafa E. Salehi, Hamid Noori, and S. M. Fakhraei, “Energy-Aware Design Space Exploration of RegisterFile for Extensible Processors,” in Proceeding of Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation(SAMOS), SAMOS, Greece, 2010, pp. 273-281.
  18. M. Kamal, N. Kazemian Amiri, A. Kamran, S.A. Hoseini, M. Dehyadegari, and H. Noori, "Dual-Purpose Custom Instruction Identification Algorithm based on Particle Swarm Optimization," in Proceeding of 21st IEEE International Conference on Application-specific Systems, Architectures and Processors(ASAP10), Rennes, France, 2010, pp. 159-166.
  19. M. Kamal, S. Koohi, S. Hessabi," A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus," in Proceeding of International CSI Computer conference, Kish Island, Persian Gulf, Iran, March 2008, pp. 90-97.
  20. M. Kamal, M. Salmani Jelodar, S. Hessabi," GABIST: A New Methodology to Find near Optimal LFSR for BIST Structure," in Proc. IEEE Intl. Conf. on Electronics, Circuits and Systems, Marrakesh, Morroco, Dec. 2007.
  21. M. Kamal, S. Koohi, S. Hessabi, ”Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs,” in Proceeding of 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Italy, September, 2007, pp. 179-187.
  22. M. Kamal, S. Koohi, S. Hessabi, ”Analyzing Capability of LFSR
    Architecture as a TPG to Reduce Power, Energy and Test Delay,” in Proceeding of 5th IEEE East-West Design & Test International Symposium, Armenia, September, 2007.
  23. Amin Farmahini Farahani, Mehdi Kamal, Seid Mehdi Fakhraie, Saeed Safari, " HW/SW partitioning using discrete particle swarm," in Proc. GLSVLSI 2007, pp. 359-364.
  24. M. Kamal and S. Kasaei. An Improved Method for Designing Morphological Filtering based on Genetic Algorithm and Wavelet Transform. In The 4th Iranian Conference on Machine Vision & Image Processing, MVIP, pages 625–632, Mashad, Iran, Feb. 2007.
  25. Amin Farmahini Farahani, Mehdi Kamal, Mehdi Salmani Jelodar, " Parallel-Genetic-Algorithm-Based HW/SW Partitioning," in Proc. PARAELEC  2006, pp. 337-342.
  26. Mehdi Salmani Jelodar, Mehdi Kamal, Seid Mehdi Fakhraie, and Majid Nili Ahmadabadi, “SOPC-based parallel genetic framework,” IEEE World Congress on Computational Intelligence, WCCI'06, Vancouver, BC, Canada, Jul. 2006.
  27. Mehdi Salmani Jelodar, Mehdi Kamal, Seid Mehdi Fakhraie, and Majid Nili Ahmadabadi, “SOPC-based genetic algorithm”, Fourteenth Iranian Conf. on Electrical Engineering, ICEE'06, Tehran, Iran, May 2006.
  28. Mehdi Kamal, Amin Farmahini, Mehdi Salmani Jelodar, “Automatic Combinational Circuit Design using Genetic Algorithm,” in 7th Conf. on Intelligent Systems, Tehran, Iran, 2005 (Persian).

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Teaching

  • Core-Based Embedded system Design
  • Data Structures & Algorithms in Electrical Engineering
  • Digital Electronic Circuits
  • VLSI
  • Low Power Integrated Circuits
  • Memory Technologies, Circuits, and Systems