Behzad Ebrahimi

ph.D.

 

behzadebrahimielec@gmail.com

Group: VLSI Device and Circuits

Personal

  • Born in Nov 1983, Mashhad, Iran.

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Education

  • 2014 until now: Postdoctoral fellow in Electrical and Electronics Engineering, University of Tehran, Tehran, Iran (Advisor: Dr. Afzali-Kusha)
  • 2009 to 2014: Ph.D. Student in Electrical and Electronics Engineering, Nano-technology, University of Tehran, Tehran, Iran, GPA 18.7/20, Thesis: Design Optimization of SRAM Cell Using Emerging Si-based Nanoscale Technologies (Advisor: Dr. Afzali-Kusha)
  • 2006 to 2009: M.Sc. Degree in Electrical and Electronics Engineering, University of Tehran, Tehran, Iran, GPA 18.84/20 (Among two top students), Thesis: Device Modeling and Optimization of SRAM in Nanoscale era (Advisor: Dr. Afzali-Kusha)
  • 2001 to 2006: B.Sc. Degree in Electrical and Electronics Engineering, University of Tehran, Tehran, Iran, GPA 15.14/20, Project: Extraction of SOI parameters using MINIMOS simulator (Advisor: Dr. Afzali-Kusha)
  • 1997-2001: High School Diploma of Physics and Mathematics, Shahid Beheshti High School(Administrated by National Organization for Development of Exceptional Students, NODET) Sabzevar, Iran, GPA 19.37/20

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Research Interests

  • Process variation tolerant design for nano-scaled VLSI circuits
  • Low power VLSI design
  • Nano-scaled transistors (including FinFET, Tunnel FET transistors) current-voltage characteristics investigation and modeling
  • SRAM cell design in nanometer technologies
  • Power transistor design and simulation

Honors

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Publications

Behzad Ebrahimi's Google Scholar page

ISI International Journal Papers

IEEE International Conference Papers

Other Publications

  • B. Ebrahimi and A. Afzali-Kusha, "FinFET SRAM Design using Dynamic Back-Gate Bias," Proc. Of the Nanotechnology Student Conference, May 2013.

  • R. Asadpour, B. Ebrahimi, and A. Afzali-Kusha, "Robust SRAM Cells Based on Asymmetric Nanoscale FinFET," Proc. Of the Nanotechnology Student Conference, May 2013.

  • M.Moradinasab, B.Ebrahimi, M. Fathipour, and B. Foroozandeh "A compact physical model for subthreshold current in nanoscale FD/SOI MOSFETs," Proc. Of the International Conference on Electronic Materials, Jul. 2008, pp. 1109.
  • B. Ebrahimi and Ali Afzali-Kusha, "Double gate based SRAM design using back gate voltage," Proc. Of the Nanotechnology Student Conference, Oct. 2008.

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Skills and Experiences

In depth practical experience with application packages such as

      Circuit Simulators: HSpice

      Device and Fabrication Simulators

      Matlab

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Teaching

  • Advanced Digital Electronics
  • VLSI
  • Nano-devices and Their Integration
  • CMOS integrated circuit design
  • Electronics Lab

     

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Work Experiences

    Summer 2004 : Electronics Lab., School of ECE, University of Tehran, Iran.

    •  Preparing Instruction papers for Lab, and devising a new set of experiments for this lab.
    •  Designing a circuit for protecting refrigerator in varying of voltage and implementation with micro 8051 in Micro LAB

    Spring 2006 Winter 2006: Pardis Novel Processing Technology Company

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